Focus on:
All days
Nov 28, 2023
Nov 29, 2023
All sessions
Welcome and Introduction
Hide Contributions
Indico style
Indico style - inline minutes
Indico style - numbered
Indico style - numbered + minutes
Indico Weeks View
Back to Conference View
Choose Timezone
Use the event/category timezone
Specify a timezone
Africa/Abidjan
Africa/Accra
Africa/Addis_Ababa
Africa/Algiers
Africa/Asmara
Africa/Bamako
Africa/Bangui
Africa/Banjul
Africa/Bissau
Africa/Blantyre
Africa/Brazzaville
Africa/Bujumbura
Africa/Cairo
Africa/Casablanca
Africa/Ceuta
Africa/Conakry
Africa/Dakar
Africa/Dar_es_Salaam
Africa/Djibouti
Africa/Douala
Africa/El_Aaiun
Africa/Freetown
Africa/Gaborone
Africa/Harare
Africa/Johannesburg
Africa/Juba
Africa/Kampala
Africa/Khartoum
Africa/Kigali
Africa/Kinshasa
Africa/Lagos
Africa/Libreville
Africa/Lome
Africa/Luanda
Africa/Lubumbashi
Africa/Lusaka
Africa/Malabo
Africa/Maputo
Africa/Maseru
Africa/Mbabane
Africa/Mogadishu
Africa/Monrovia
Africa/Nairobi
Africa/Ndjamena
Africa/Niamey
Africa/Nouakchott
Africa/Ouagadougou
Africa/Porto-Novo
Africa/Sao_Tome
Africa/Tripoli
Africa/Tunis
Africa/Windhoek
America/Adak
America/Anchorage
America/Anguilla
America/Antigua
America/Araguaina
America/Argentina/Buenos_Aires
America/Argentina/Catamarca
America/Argentina/Cordoba
America/Argentina/Jujuy
America/Argentina/La_Rioja
America/Argentina/Mendoza
America/Argentina/Rio_Gallegos
America/Argentina/Salta
America/Argentina/San_Juan
America/Argentina/San_Luis
America/Argentina/Tucuman
America/Argentina/Ushuaia
America/Aruba
America/Asuncion
America/Atikokan
America/Bahia
America/Bahia_Banderas
America/Barbados
America/Belem
America/Belize
America/Blanc-Sablon
America/Boa_Vista
America/Bogota
America/Boise
America/Cambridge_Bay
America/Campo_Grande
America/Cancun
America/Caracas
America/Cayenne
America/Cayman
America/Chicago
America/Chihuahua
America/Ciudad_Juarez
America/Costa_Rica
America/Creston
America/Cuiaba
America/Curacao
America/Danmarkshavn
America/Dawson
America/Dawson_Creek
America/Denver
America/Detroit
America/Dominica
America/Edmonton
America/Eirunepe
America/El_Salvador
America/Fort_Nelson
America/Fortaleza
America/Glace_Bay
America/Goose_Bay
America/Grand_Turk
America/Grenada
America/Guadeloupe
America/Guatemala
America/Guayaquil
America/Guyana
America/Halifax
America/Havana
America/Hermosillo
America/Indiana/Indianapolis
America/Indiana/Knox
America/Indiana/Marengo
America/Indiana/Petersburg
America/Indiana/Tell_City
America/Indiana/Vevay
America/Indiana/Vincennes
America/Indiana/Winamac
America/Inuvik
America/Iqaluit
America/Jamaica
America/Juneau
America/Kentucky/Louisville
America/Kentucky/Monticello
America/Kralendijk
America/La_Paz
America/Lima
America/Los_Angeles
America/Lower_Princes
America/Maceio
America/Managua
America/Manaus
America/Marigot
America/Martinique
America/Matamoros
America/Mazatlan
America/Menominee
America/Merida
America/Metlakatla
America/Mexico_City
America/Miquelon
America/Moncton
America/Monterrey
America/Montevideo
America/Montserrat
America/Nassau
America/New_York
America/Nome
America/Noronha
America/North_Dakota/Beulah
America/North_Dakota/Center
America/North_Dakota/New_Salem
America/Nuuk
America/Ojinaga
America/Panama
America/Paramaribo
America/Phoenix
America/Port-au-Prince
America/Port_of_Spain
America/Porto_Velho
America/Puerto_Rico
America/Punta_Arenas
America/Rankin_Inlet
America/Recife
America/Regina
America/Resolute
America/Rio_Branco
America/Santarem
America/Santiago
America/Santo_Domingo
America/Sao_Paulo
America/Scoresbysund
America/Sitka
America/St_Barthelemy
America/St_Johns
America/St_Kitts
America/St_Lucia
America/St_Thomas
America/St_Vincent
America/Swift_Current
America/Tegucigalpa
America/Thule
America/Tijuana
America/Toronto
America/Tortola
America/Vancouver
America/Whitehorse
America/Winnipeg
America/Yakutat
Antarctica/Casey
Antarctica/Davis
Antarctica/DumontDUrville
Antarctica/Macquarie
Antarctica/Mawson
Antarctica/McMurdo
Antarctica/Palmer
Antarctica/Rothera
Antarctica/Syowa
Antarctica/Troll
Antarctica/Vostok
Arctic/Longyearbyen
Asia/Aden
Asia/Almaty
Asia/Amman
Asia/Anadyr
Asia/Aqtau
Asia/Aqtobe
Asia/Ashgabat
Asia/Atyrau
Asia/Baghdad
Asia/Bahrain
Asia/Baku
Asia/Bangkok
Asia/Barnaul
Asia/Beirut
Asia/Bishkek
Asia/Brunei
Asia/Chita
Asia/Choibalsan
Asia/Colombo
Asia/Damascus
Asia/Dhaka
Asia/Dili
Asia/Dubai
Asia/Dushanbe
Asia/Famagusta
Asia/Gaza
Asia/Hebron
Asia/Ho_Chi_Minh
Asia/Hong_Kong
Asia/Hovd
Asia/Irkutsk
Asia/Jakarta
Asia/Jayapura
Asia/Jerusalem
Asia/Kabul
Asia/Kamchatka
Asia/Karachi
Asia/Kathmandu
Asia/Khandyga
Asia/Kolkata
Asia/Krasnoyarsk
Asia/Kuala_Lumpur
Asia/Kuching
Asia/Kuwait
Asia/Macau
Asia/Magadan
Asia/Makassar
Asia/Manila
Asia/Muscat
Asia/Nicosia
Asia/Novokuznetsk
Asia/Novosibirsk
Asia/Omsk
Asia/Oral
Asia/Phnom_Penh
Asia/Pontianak
Asia/Pyongyang
Asia/Qatar
Asia/Qostanay
Asia/Qyzylorda
Asia/Riyadh
Asia/Sakhalin
Asia/Samarkand
Asia/Seoul
Asia/Shanghai
Asia/Singapore
Asia/Srednekolymsk
Asia/Taipei
Asia/Tashkent
Asia/Tbilisi
Asia/Tehran
Asia/Thimphu
Asia/Tokyo
Asia/Tomsk
Asia/Ulaanbaatar
Asia/Urumqi
Asia/Ust-Nera
Asia/Vientiane
Asia/Vladivostok
Asia/Yakutsk
Asia/Yangon
Asia/Yekaterinburg
Asia/Yerevan
Atlantic/Azores
Atlantic/Bermuda
Atlantic/Canary
Atlantic/Cape_Verde
Atlantic/Faroe
Atlantic/Madeira
Atlantic/Reykjavik
Atlantic/South_Georgia
Atlantic/St_Helena
Atlantic/Stanley
Australia/Adelaide
Australia/Brisbane
Australia/Broken_Hill
Australia/Darwin
Australia/Eucla
Australia/Hobart
Australia/Lindeman
Australia/Lord_Howe
Australia/Melbourne
Australia/Perth
Australia/Sydney
Canada/Atlantic
Canada/Central
Canada/Eastern
Canada/Mountain
Canada/Newfoundland
Canada/Pacific
Europe/Amsterdam
Europe/Andorra
Europe/Astrakhan
Europe/Athens
Europe/Belgrade
Europe/Berlin
Europe/Bratislava
Europe/Brussels
Europe/Bucharest
Europe/Budapest
Europe/Busingen
Europe/Chisinau
Europe/Copenhagen
Europe/Dublin
Europe/Gibraltar
Europe/Guernsey
Europe/Helsinki
Europe/Isle_of_Man
Europe/Istanbul
Europe/Jersey
Europe/Kaliningrad
Europe/Kirov
Europe/Kyiv
Europe/Lisbon
Europe/Ljubljana
Europe/London
Europe/Luxembourg
Europe/Madrid
Europe/Malta
Europe/Mariehamn
Europe/Minsk
Europe/Monaco
Europe/Moscow
Europe/Oslo
Europe/Paris
Europe/Podgorica
Europe/Prague
Europe/Riga
Europe/Rome
Europe/Samara
Europe/San_Marino
Europe/Sarajevo
Europe/Saratov
Europe/Simferopol
Europe/Skopje
Europe/Sofia
Europe/Stockholm
Europe/Tallinn
Europe/Tirane
Europe/Ulyanovsk
Europe/Vaduz
Europe/Vatican
Europe/Vienna
Europe/Vilnius
Europe/Volgograd
Europe/Warsaw
Europe/Zagreb
Europe/Zurich
GMT
Indian/Antananarivo
Indian/Chagos
Indian/Christmas
Indian/Cocos
Indian/Comoro
Indian/Kerguelen
Indian/Mahe
Indian/Maldives
Indian/Mauritius
Indian/Mayotte
Indian/Reunion
Pacific/Apia
Pacific/Auckland
Pacific/Bougainville
Pacific/Chatham
Pacific/Chuuk
Pacific/Easter
Pacific/Efate
Pacific/Fakaofo
Pacific/Fiji
Pacific/Funafuti
Pacific/Galapagos
Pacific/Gambier
Pacific/Guadalcanal
Pacific/Guam
Pacific/Honolulu
Pacific/Kanton
Pacific/Kiritimati
Pacific/Kosrae
Pacific/Kwajalein
Pacific/Majuro
Pacific/Marquesas
Pacific/Midway
Pacific/Nauru
Pacific/Niue
Pacific/Norfolk
Pacific/Noumea
Pacific/Pago_Pago
Pacific/Palau
Pacific/Pitcairn
Pacific/Pohnpei
Pacific/Port_Moresby
Pacific/Rarotonga
Pacific/Saipan
Pacific/Tahiti
Pacific/Tarawa
Pacific/Tongatapu
Pacific/Wake
Pacific/Wallis
US/Alaska
US/Arizona
US/Central
US/Eastern
US/Hawaii
US/Mountain
US/Pacific
UTC
Save
Europe/Amsterdam
English (United States)
Deutsch (Deutschland)
English (United Kingdom)
English (United States)
Español (España)
Français (France)
Polski (Polska)
Português (Brasil)
Türkçe (Türkiye)
Čeština (Česko)
Монгол (Монгол)
Українська (Україна)
中文 (中国)
Login
NanoXplore's 5th BRAVE Days
from
Tuesday, November 28, 2023 (9:00 AM)
to
Wednesday, November 29, 2023 (4:00 PM)
Monday, November 27, 2023
Tuesday, November 28, 2023
9:00 AM
Event Opening / Reception
Event Opening / Reception
9:00 AM - 9:30 AM
9:30 AM
Welcome and Introduction
-
Edouard Lepape
Welcome and Introduction
Edouard Lepape
9:30 AM - 9:45 AM
9:45 AM
Company Update
-
Edouard Lepape
Company Update
Edouard Lepape
9:45 AM - 10:15 AM
10:15 AM
Impulse : Year One
-
Alp KILIC
(
Nanoxplore
)
Impulse : Year One
Alp KILIC
(
Nanoxplore
)
10:15 AM - 11:15 AM
11:15 AM
Break
Break
11:15 AM - 12:00 PM
12:00 PM
ESA Contribution
-
David Merodio Codinachs
(
ESA
)
ESA Contribution
David Merodio Codinachs
(
ESA
)
12:00 PM - 12:30 PM
12:30 PM
BRAVE FPGA, GRLIB and GR765
-
Sandi Habinc
(
Cobham Gaisler AB
)
BRAVE FPGA, GRLIB and GR765
Sandi Habinc
(
Cobham Gaisler AB
)
12:30 PM - 1:00 PM
Frontgrade contribution
1:00 PM
Lunch Break
Lunch Break
1:00 PM - 2:30 PM
2:30 PM
Harnessing the Power of HDL Coder and Collaborative Integration with NanoXplore
-
Yanitsa Stoyanova
(
Airbus
)
Stephan van Beek
(
MathWorks
)
Harnessing the Power of HDL Coder and Collaborative Integration with NanoXplore
Yanitsa Stoyanova
(
Airbus
)
Stephan van Beek
(
MathWorks
)
2:30 PM - 3:00 PM
In the ever-evolving field of Field-Programmable Gate Array (FPGA) development, the synergy between advanced design tools and collaborative partnerships holds immense potential. This talk explores the transformative capabilities of HDL Coder, a powerful toolset for generating synthesizable HDL code from MATLAB and Simulink models, and its integration with NanoXplore, a leading provider of high-performance FPGA solutions. The talk highlights the collaborative efforts between HDL Coder and NanoXplore, showcasing their combined expertise in FPGA architecture and design optimization. A specific use-case in space missions, focusing on satellites, demonstrates how this integration enables efficient implementation of complex functionalities while overcoming space, power, and reliability challenges. Attendees will gain insights into successful satellite missions leveraging this collaboration, resulting in improved performance, reduced development time, and increased reliability in space environments. FPGA designers, algorithm developers, and system architects will learn how to leverage HDL Coder and NanoXplore for advanced space mission development.
3:00 PM
Speeding up DO-178C Safety Certification with Trace-based Code Coverage
-
Ladislav Řehák
(
Lauterbach
)
Speeding up DO-178C Safety Certification with Trace-based Code Coverage
Ladislav Řehák
(
Lauterbach
)
3:00 PM - 3:30 PM
Collecting code coverage information is required for all the common software certification processes, including the one defined by DO-178C. This is usually a challenge because traditional code coverage measurement requires extensive code instrumentation which has all kinds of side effects like (additional) memory consumption, slowing down the execution, and much more. After discussing the overall added value of Lauterbach’s real-time-trace debug features for developers of any embedded application, this presentation explores the advantages of Trace-based Code Coverage for integration and system tests and demonstrates a practical example using an NG Ultra SoC by NanoXplore. We will observe and discuss the advantages of minimal or even zero code instrumentation used for Lauterbach’s new trace-based measurement method compared with the traditional source code instrumentation.
3:30 PM
Break
Break
3:30 PM - 4:00 PM
4:00 PM
Star Dundee Contribution
-
Marti Farras Casas
(
STAR-Dundee
)
Star Dundee Contribution
Marti Farras Casas
(
STAR-Dundee
)
4:00 PM - 4:30 PM
SpaceFibre (ECSS-E-ST-50-11C) is an evolution of SpaceWire, being backwards compatible with SpaceWire at the packet level. SpaceFibre is a very high-performance, high-reliability and high-availability network technology specifically designed to meet the needs of modern space applications where very high throughput is required. It provides point-to-point and networked interconnections at Gigabit rates— more than 6.25 Gbit/s per lane for current FPGAs, with multi-lane allowing to reach up to 16 times the speed of a single lane —with Quality of Service (QoS) and Fault Detection, Isolation and Recovery (FDIR). SpaceFibre NORBY and OPS-SAT technology demonstrators have already flown SpaceFibre, with more missions in both Europe and the USA currently designing or planning to use SpaceFibre. STAR-Dundee has developed a complete family of SpaceWire and SpaceFibre IP cores fully compliant with these ECSS standards. A new generation of radiation-tolerant FPGAs is emerging to cope with the ever-growing processing power required by newer missions, the BRAVE FPGAs family is a good example of this new generation of FPGAs. SpaceFibre operation requires serial transceivers, which are already inbuilt in modern FPGAs. The SpaceFibre IPs have been adapted to take advantage of the specific transceivers and memory blocks offered by these new FPGAs. In this work we present the effort done to ensure that STAR-Dundee SpaceFibre IP cores work on the BRAVE FPGAs including simulation results from the verification with simulation models of the transceivers, post-synthesis resource utilisation and simulation of SpaceFibre IP and hardware tests done in the process.
4:30 PM
Moon exploration with FUSIO RT- A scalable and configurable computer core
-
Pierre Berthet
Moon exploration with FUSIO RT- A scalable and configurable computer core
Pierre Berthet
4:30 PM - 5:00 PM
5:00 PM
Break
Break
5:00 PM - 5:30 PM
5:30 PM
Cocktail Party
Cocktail Party
5:30 PM - 9:00 PM
Wednesday, November 29, 2023
8:30 AM
Coffee and mingling
Coffee and mingling
8:30 AM - 9:30 AM
9:30 AM
NEORV32 runs on NG-MEDIUM
-
Klemen Bravhar
NEORV32 runs on NG-MEDIUM
Klemen Bravhar
9:30 AM - 10:00 AM
Nanoxplorer’s Field Programmable Gate Arrays (FPGA) and tools, which help a user integrate their Register Transfer Level (RTL) projects in Nanoxplorer (NX) FPGA portfolio, matured to the point, where a user with few clicks in Graphical User Interface (GUI) Impulse or python environment (NxPython3) build their RTL code for BRAVE FPGAs. The main goal of our practice was to evaluate the latest NX tools and test them with a complex open-source RISC V core (NEORV32 RISC-V processor) and integrate NEORV32 on NgMedium BRAVE FPGA. NEORV32 RISC-V processor is a customizable microcontroller (System on Chip – SoC) with a 32-bit processor which supports all RISC-V instructions, and its RTL is written in VHDL and Verilog Hardware Description Language (HDL). The NEORV32 processor core bases on RISC-V instruction architecture, and a user can attach to the core various peripheries such as UART, SPI, WatchDog timer, etc. The synthesis and integration steps were given in the Python script and then run with NxPython3. After the tool successfully generated bitstream for NgMedium FPGA, we uploaded it on the NgMedium development board. As with any other processor running on an FPGA, evaluation and benchmarking of the NEORV32 synthesized version was with software (SW), which runs a robot spider with four legs, and each leg has three joints. The spider movements are given in the cartesian and polar coordinate system and then described in C language. After compiling C code, SW required 32kB of Memory. To fit the spider application in the NEORV32 processor, the processor consumed around 12% of logical/sequential components and 22 Block RAM for instruction and data memory. Implemented NEORV32 core runs with a clock frequency of 37.5MHz, which is sufficient for the program to execute periodically every 20ms.
10:00 AM
RISC-V for payload Control and Data Processing
-
Gerard Rauwerda
(
Technolution B.V.
)
RISC-V for payload Control and Data Processing
Gerard Rauwerda
(
Technolution B.V.
)
10:00 AM - 10:30 AM
The FreNox RISC-V microcontroller IP has its heritage in numerous products for high-assurance and high-reliable security applications for data line encryption and network domain separation (i.e. NLD/EU/NATO-restricted). As a founding member of the RISC-V Foundation, Technolution has designed and implemented the FreNox RISC-V processor family. The FreNox RISC-V microcontroller IP has been integrated in numerous FPGA devices. We also ported the full AXI-4-based FreNox RISC-V system-on-chip into the radiation-hardened NanoXplore NG-Medium device, and have created a full interactive demonstration; through the SpW-interface we upload software in the RISC-V SoC, allowing the user to play the "Space Invaders" game on the NG-Medium board. We keep improving our RISC-V platform; for instance with processor-agnostic simple gdb remote interface, implemented and demonstrated in the FreNox RISC-V processor. We have designed and implemented a simple gdb remote interface for multiple platforms to make gdb over a serial link a practical proposition for embedded microcontroller use. The implementation comes with limited hardware overhead, and has been included in our full interactive "Space Invaders" demonstration. Under the Key Digital Technologies Joint Undertaking (KDT JU) TRISTAN project the RISC-V microcontroller design is being iterated for increased security and robustness for space application, such as implementing error and security checkers, lock-step operation, FDIR control and radiation testing. For SmallSat payload control and data processing, we foresee wide use of reconfigurable FPGA technology. So, we have started the development of a novel payload control and data processing unit that is able to serve the evolving SmallSat market and is a perfect-fit solution for compact instrument developers. The proposed modular payload control and data processing architecture provides a good separation of concerns between instrument developers and platform provider allowing short time-to-orbit of payloads and missions. It offers a combination of FPGA-based instrument control functions, interface flexibility and powerful data processing capabilities. Telemetry and telecommand handling and most instrument control functions will be covered by our RISC-V softcore microcontroller.
10:30 AM
FPG-AI: A TECHNOLOGY INDEPENDENT FRAMEWORK FOR EDGE AI DEPLOYMENT ONBOARD SATELLITE, AND ITS CHARACTERISATION ON NANOXPLORE FPGAS
-
Pietro Nannipieri
Pietro Nannipieri
(
University of Pisa
)
FPG-AI: A TECHNOLOGY INDEPENDENT FRAMEWORK FOR EDGE AI DEPLOYMENT ONBOARD SATELLITE, AND ITS CHARACTERISATION ON NANOXPLORE FPGAS
Pietro Nannipieri
Pietro Nannipieri
(
University of Pisa
)
10:30 AM - 11:00 AM
In recent years, research in the space community has shown a growing interest in AI, mostly driven by systems miniaturization and commercial competition. FPGA have proven to be competitive accelerators for these algorithms and works proposing methods for automating the design on these devices have acquired relevance. The common purpose is to enable a wide range of users without specific skills to accelerate AI models on FPGA with reduced development times.This presentation will focus on the characterization of FPG-AI, a novel technology-independent toolflow for automating AI deployment on FPGA, on NanoXplore devices. We will present preliminary information on the achieved performances in terms of computational power and resource consumption on a representative use case scenario.
11:00 AM
Break
Break
11:00 AM - 11:30 AM
11:30 AM
Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs
-
Luca Sterpone
(
Politecnico di Torino
)
Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs
Luca Sterpone
(
Politecnico di Torino
)
11:30 AM - 12:00 PM
Radiation-Hardened-By-Design (RHBD) FPGAs have gained a lot of attention thanks to their excellent compromise between costs and performance. Being of very limited use due to a lack of performance a few years ago, these devices are now capable of implementing a wide range of applications requiring high computational capabilities. This work describes an implementation of a Very Long Instruction Word (VLIW) soft-core convolutional accelerator in the NanoXplore RHBD NG-Medium chip. Feasibility and timing performances have been analyzed in order to discover whether and how multi-core solutions can affect parallel acceleration. Placement also showed to heavily affect the delays, up to 70% more, based on the proximity to the output buffers.
12:00 PM
Exploring the Latest High-Level Synthesis Results with Bambu: Insights from the HERMES Project's Use Cases
-
Fabrizio Ferrandi
(
Politecnico di Milano
)
Exploring the Latest High-Level Synthesis Results with Bambu: Insights from the HERMES Project's Use Cases
Fabrizio Ferrandi
(
Politecnico di Milano
)
12:00 PM - 12:30 PM
Europe is working on improving competitiveness in the space services sector by developing radiation-resistant, high-performance microprocessors and simplifying the deployment of complex applications. The HERMES project aims to achieve a technology readiness level of 6 for the rad-hard NG-ULTRA FPGA and supports multicore software programming and FPGA acceleration. The talk will focus on the latest developments and results obtained by Bambu high-level synthesis tool on the HERMES project's use cases. Specifically, the presentation will highlight how Bambu optimizes specific patterns common in the HERMES use cases.
12:30 PM
XNG versus bare-metal performance on NG-Ultra: a comprehensive comparison
-
Antonio García Vilanova
(
FentISS
)
XNG versus bare-metal performance on NG-Ultra: a comprehensive comparison
Antonio García Vilanova
(
FentISS
)
12:30 PM - 1:00 PM
A comparison of the NG-Ultra high-level performance capabilities in both bare-metal and under the XNG hypervisor for NG-Ultra both in a monocore and in a multicore environment will be carried out, providing valuable insights into a high-degree optimization and unlocking the full potential of this hardware.
1:00 PM
Lunch Break
Lunch Break
1:00 PM - 2:30 PM
2:30 PM
GMV and BRAVE FPGAs: From Studies to Flight Hardware use
-
Rubén Domingo Torrijos
(
GMV
)
GMV and BRAVE FPGAs: From Studies to Flight Hardware use
Rubén Domingo Torrijos
(
GMV
)
2:30 PM - 3:00 PM
3:00 PM
SYSGO, PikeOS and NG-ULTRA compatibility
-
Thierry Maudire
(
SYSGO S.A.S.
)
SYSGO, PikeOS and NG-ULTRA compatibility
Thierry Maudire
(
SYSGO S.A.S.
)
3:00 PM - 3:30 PM
A brief introduction of SYSGO and its flagship product PikeOS for MPU will be presented, following by a description of the current functionalities available with PikeOS for MPU on the NG-ULTRA development kit platform from NanoXplore: runtime features, as well as development tooling supported. In addition, a live demonstrator featuring PikeOS for MPU running on each of the 4 cores of the NG-Ultra platform will be demonstrated.
3:30 PM
Thanks and Farewells
Thanks and Farewells
3:30 PM - 4:00 PM