Speaker
Dr
Chafika BELAMRI
(Satellite Development Center)
Description
In space radiation environment, SEU mitigation is crucial to guarantee total reliable operation of memory and FPGA devices. This paper presents the design of a an EDAC system based on the combination of partial TMR and the Quasi-cyclic codes implemented in SRAM-based FPGAs to protect SRAM memories against Single Event Upsets. Experimental results show that the proposed EDAC has smaller delay, area, and power overheads over standard EDAC schemes.
Primary authors
Youcef BENTOUTOU
(Satellite Development Center)
Dr
Chafika BELAMRI
(Satellite Development Center)
Mrs
Malika BENDOUDA
(Satellite Development Center)
Dr
Chahira SERIEF
(Satellite Development Center)
