AMICSA 2025

Session

Phase Locked Loop

PLL

16 Jun 2025, 16:30

Rectorship building (Universidade Nova de Lisboa)

Description

Radiation-Tolerant PLL Design for Frequency Stability in Space Systems

2. Jitter Measurement Results of DARE22 Phase-Locked Loop

SinNyoung Kim (imec)

16/06/2025, 16:30

Custom Cell, Circuit, and System Design

The DARE22G Phase-Locked Loop (PLL) has been designed in a 22nm Fully Depleted Silicon On Insulator (FD-SOI). It is required to be not only a radiation-hardened, but also low jitter PLL, with a target period jitter of less than 1ps for a 3GHz output frequency. As the application of the DARE22G PLL is in a digital system, period jitter is selected as a requirement in this design, instead of...

7. ITAR-free Multi-Output Low Phase Noise Radiation Hardened by Design PLL

Dr Maarten Strackx (Magics Technologies)

16/06/2025, 17:00

Custom Cell, Circuit, and System Design

A fully integrated radiation-hardened all-digital frequency synthesizer, designed in a commercial CMOS technology, is presented in this paper. Radiation hardness by design is implemented in all analog and digital blocks and throughout the chip architecture. The simulated normalized phase noise is at -230 dBc/Hz, hence outperforms its measured prototype of -210 dBc/Hz. The synthesizer can work...