AMICSA 2025

16 Jun 2025, 08:05 → 18 Jun 2025, 15:35 Europe/Berlin

Rectorship building (Universidade Nova de Lisboa)

10th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications

16 – 18 June 2025

AMICSA offers an international platform to present and discuss recent advancements in analogue, mixed-signal, and custom microcircuits designed for harsh environments. The scope focuses on resilience to radiation, durability against aging, and reliable performance in cryogenic conditions.

The workshop's program is organized into the following key tracks:

Needs and Requirements for Future Missions

• Overview of the specific demands and challenges posed by upcoming space applications.
• Focus on aligning microcircuit design goals with mission objectives.

Radiation-Hardened Technologies

• Advances in CMOS and non-CMOS solutions for radiation resilience

• Exploration of advanced node technologies, including UDSM and FinFET architectures

Methodologies for Radiation Hardening

• Techniques for radiation hardening at cell, circuit, and system levels
• Innovative approaches to improve reliability under extreme conditions

Intellectual Property and Re-usability

• Creation and integration of analogue and mixed-signal IP cores
• Development of reusable full custom digital IP cores and digital cell libraries

Radiation Effects

• In-depth exploration of radiation effect mechanisms
• Advanced modelling techniques to predict radiation impacts

Radiation Test Results

• Comparative analysis of simulation and measurement data

• Evaluation of test methodologies for validating radiation tolerance

Qualification

• Adherence to ESCC and ECSS standards for component and system qualification
• Key practices for ensuring compliance and reliability

Space Applications

• Presentation of practical use cases and mission-specific applications
• Exploration of the interplay between design and operational environments

In-Orbit Experiences and Flight Heritage

• Insights from real-world deployments of microcircuits
• Lessons learned and performance metrics from flight-proven systems

ESA - DPNR.pdf

Monday 16 June

09:00 → 09:30 AMICSA: Registration

Introduction and Welcome

09:30 → 09:45 AMICSA: Welcome

Introduction and Welcome

Conveners: Boris Glass (ESA), João Goes (UNINOVA)

09:30 Welcome AMICSA 2025

Speakers: Boris Glass (ESA), João Goes (UNINOVA)

amicsa_welcome_2025_bg.pptx

09:45 → 10:30 Keynote

Pushing the Frontiers of Microelectronics for Space: Challenges, Trends, and Vision

09:45 Extreme-Environment ASIC Design For Scientific Instruments

This talk will provide an overview of recent work at Brookhaven National Laboratory (BNL) on analog and mixed-signal application-specific integrated
circuits (ASICs) designed to operate reliably in extreme environments (high-radiation, cryogenic, or high-temperature). Several examples of such ASICs
and their use cases in various high-energy and nuclear physics experiments will be discussed. One case study will focus on the design and testing of
front-end CMOS ASICs operating at liquid argon temperature (85K) for the Deep Underground Neutrino Experiment (DUNE). These chips provide low-noise
charge readout within noble-liquid time projection chambers (TPCs) that aim to reconstruct the three-dimensional trajectories of incident particles and/or
their energy distribution with high spatial, temporal, and energy resolution. As another example, a serial-powered architecture and associated radiation-
hardened ancillary ASIC in partially-depleted silicon-on-insulator (PDSOI) technology will be discussed for interfacing to large-area monolithic active pixel
sensors (MAPS). Arrays of such large-area MAPS are being developed for high-precision particle tracking within the ePIC detector of the planned Electron Ion
Collider (EIC). Finally, the design of adaptive line driver ASICs with configurable pre-emphasis will be discussed for wired data transmission across ultra-thin
radio-pure cables. Such high-loss cables are required to read out cryogenic detectors immersed in noble liquids (liquid argon or xenon) for a variety of rare-
event physics experiments. Potential applications of the proposed ASICs to space-borne experiments will also be discussed if time permits.

Speaker: Soumyajit Mandal (Brookhaven National Laboratory)

Mandal_AMICSA_2025.pptx

10:30 → 11:00 Coffee

11:00 → 13:00 Reusable Design Libraries

Reusable Mixed-Signal IP and Library Development

11:00 Characterization and Measurement of the SET Pulse Duration of the DARE65T Standard Cell Library

Characterization and Measurement of the SET Pulse Duration of the DARE65T Standard Cell Library
Laurent Berti, Bastien Vignon, El Hafed Boufouss, Maxim Gorbunov, Zheyi Li, Marcel van de Burgwal
Imec, Leuven, Belgium
Tracks:
• Radiation-hardened technologies
• Radiation Test Results

To properly and optimally harden a design for a specific space mission, it is crucial to identify the critical parts of the circuit (e.g., reset and clock signals, PLL configuration signals, critical state machines, ...) and the associated SEE probability (cross section). For low error rate requirements, certain parts of the circuit may need specific hardening. Digital design hardening can be achieved through various methods:
Drive strength increase
Triplication (local, distributed, global TMR, etc.)
Error Correction Codes (ECC)
SET filtering
...
SET filtering is the most efficient way to harden a digital signal in terms of area and power, but it comes at the cost of speed reduction as SET filters operate as a delay cell, decreasing setup and hold margin in the paths where they are inserted. To minimize the margin lost due to SET filtering, it is important to have an accurate value for the SET duration.

SET characterization test structure
The test structure used to measure the cross-section and the SET duration is shown in Figure 1. On the left are the victims: chains of 16 or 32 cells. Each chain is limited to 32 cells connected in series to avoid significant pulse broadening (evaluated at 1-2 ps per victim on such technology) affecting the measurement result. All victim chains are combined using a NAND/NOR combiner, designed to be well-balanced to avoid pulse distortion. The combiner drives an array of SET filters with filtering windows increasing from 50 ps to 2 ns in steps of 50 ps. This approach allows for simultaneous measurement of the SET duration and validation of the SET filter.
As the combiner is sensitive to SET, a second combiner has been added in parallel to detect if the captured event originates from the victims or the combiner.

Figure 1: test structure to measure the cross section and the SET duration

The pulses propagating through the filter bank are captured with RS-latches, which are compressed into a 6-bit value with a thermometric encoder. The RS latch content is read and reset every 10 ms (100Hz). This sampling rate balances the readout bandwidth and the probability of a double hit between consecutive readings. The sensitive area of each set of victims is approximately 1100 µm², resulting in around 100 hits after 15 minutes irradiation with a flux of 10k ions/(s*cm²), equating to 1 hit on the sensitive area every 9 seconds. As each strike is independent, the probability of a double strike during 10 ms can be calculated using the Poisson distribution:

P(k=2,10ms)=(λ^k e^(-λ))/k!=6.04×10^(-7)

The estimated number of the double strikes appearing for 15 minutes of beam is equal to
6.04×10^(-7)×900/0.01=0.054, this number is well below the number of single events expected (100) and thus can be neglected.

Cross section results
Here below are the some measurement results for the inverter INVD1. Other results will be shared in the final version of this paper.

Figure 2: INVD1 Low Vth cross section (L=60nm on the left, L=70nm on the right)

LET
(MeV.mg-1.cm2) Cross section (cm2)
HVT60N HVT70N LVT60N LVT70N SVT60N SVT70N
7.2 1.14E-05 1.18E-05 6.65E-06 7.85E-06 9.52E-06 1.11E-05
13.3 1.88E-05 1.80E-05 1.51E-05 1.63E-05 1.79E-05 1.80E-05
24.5 2.40E-05 2.51E-05 2.04E-05 2.07E-05 2.12E-05 2.23E-05
33.5 3.64E-05 3.55E-05 2.89E-05 3.20E-05 3.12E-05 3.34E-05
48.5 3.42E-05 3.54E-05 2.95E-05 2.99E-05 3.19E-05 3.26E-05
66.3 5.49E-05 5.34E-05 4.75E-05 4.92E-05 5.09E-05 5.03E-05
Table 1: Cross section (N.U.) of the INVD1 versus gate length and Vth flavor
Pulse width measurement distribution

Figure 3: INVD1 pulse width distribution for different gate length (60nm and 70nm) and for different Vth flavor (low, standard and high)
The Figure 3 show the distribution of pulse width for different flavor of the DARE65 INVD1 at 7.2 and 66 Mev*cm2/mg. The first group HVT60N till LVT70N show the number of SET observed having a duration between 0 and 50 ps, the second group show the number of SET observed having a duration between 50 and 100 ps.....

Conclusion
The test structure proposed in this abstract provide an accurate distribution of the SET pulse width and validate at the same time the SET filter cell to use to filter it.
In the complete paper, other measurement results will be added (e.g. more LET: 7.2, 13.3, 24.5, 33.5, 48.5 and 66.3 Mev*cm2/mg and gates) and a comparison of the SET duration between the different gates flavor will be detailed.

Speaker: Laurent Berti (IMEC)

AMICSA 2025 DARE65T SET Characterization Paper.pdf

AMICSA 2025 DARE65T SET characterization Presentation.pdf

AMICSA 2025 DARE65T SET characterization Presentation.pptx

11:30 Radiation Hardening by Design Concepts for 7-nm FinFET Technologies

Ultra deep-submicron (UDSM) technologies are widely recognized for satellite constellations and other aerospace applications. Besides the advanced performance characteristics, 7-nm FinFET technology represents a local minimum in alpha-particle Single-Event Rate (SER) compared to the previous and 5-nm nodes, making the technology very attractive. However, the extreme complexity of design rules for this technology level makes the possibility of design-level radiation hardening questionable. The design concepts, whose effectiveness was proven in mature technologies, either become ineffective or require additional considerations. Compared to mature technologies, the FinFET process requires much more placing and routing optimization because of the drastically increased importance of metal and via resistances and capacitances. Enhanced design complexity motivates designers to search for simpler and more effective solutions. Rad-hard IC platform development needs a deep understanding of technology features, weak points, and the “digital-on-top” design flow requirements. For example, the minimizing area of the library element might be ineffective due to the resulting silicon area utilization due to the strict rules of placing and routing.

INFINIT (Irradiation assessment of N7 FINfet technology for Innovative digital Telecom applications) project is aimed at gaining a deep understanding of the 7-nm FinFET process technology for use in digital space applications. Within the project scope, two test vehicles, analog (RETVA) and digital (RETVD), were designed. The former contains elementary devices (MOSFETs, BJTs, resistors, etc.) and will be used for Total Ionizing Dose (TID) tests, which would shed light on the technology-related degradation mechanisms. The latter consists of SRAM blocks, shift registers, combinatorial cells, etc. The objective of RETVD is to test the sensitivity to Single-Event Effects (SEE) as well as to TID.

We designed a D-flip-flop based on the principles of multi-bit flip-flops with integrated majority voters for the Triple Modular Redundancy (TMR) scheme. The approach is applied to 6-bit flip-flop, which together with two majority voters gives 2-bit SEU-tolerant flip-flop unit. In a multi-bit flip-flop (MBFF), the primary and secondary latches of different “bits” are interleaved to achieve better parameter matching and optimize the timings. It is important for TMR that the copies of data are located far enough from each other to prevent the simultaneous effect from one charged particle. The interleaving of multiple bits provides this kind of node separation “naturally”: the primary and secondary latches are localized near the input (D) and output pins (Q) respectively, and the farthest nodes can be connected to make the TMR configuration. The minimal achieved separation distance is estimated as ∼1.0 μm, which will be validated during SEE tests of the RETVD. The preliminary validation of the design effectiveness was provided by means of TFIT (Transistor Failure In Time) tool developed by IROC Technologies.

We discuss the design trade-offs and compare the performance parameters of single- and multi-bit D-flip-flops from the standard library with the designed 2-bit TMR and 1-bit (Dual Interlocked Cell-based (DICE) DFFs. The nodal separation in DICE cell leads to 13% loss in the speed, which is comparable with 15% loss in area-minimized DICE solution without separation reported in literature. For 2-bit TMR DFF, the performance degradation is lower than for DICE DFF, while the SEU sensitivity is at least comparable due to the sensitive node separation. The average power per bit is about 3 times higher for 2-bit TMR DFF compared to 1-bit of the standard 6-bit DFF. The average delay is comparable with that of standard 2-bit DFF. TCAD simulations are planned to be provided in the middle of 2025. The heavy ion test campaign is planned for the second half of 2025.

Speaker: Maxim Gorbunov (imec)

gorbunov_AMICSA2025.pdf

INFINIT_AMICSA_final.pdf

INFINIT_AMICSA_v2.pdf

12:00 Evaluation of the DARE65T platform: technology study, IP library development and Demonstrator ASIC design

Although first introduced in 2005, the 65nm node still operates in the sweet spot of design complexity, performance, costs and applicability of aerospace grade ASICs. The DARE65T platform implements a complete library of digital and mixed signal IPs, that accommodate a Radiation Hardened By Design (RHBD) regular design flow and manufacture ASICs in commercial technology. To apply the right mitigation techniques against radiation effects, a test vehicle with technology components was characterized and irradiated under Total Ionizing Dose (TID). With two additional test vehicles, all developed IPs were characterized and irradiated under both TID and Single Event Effects (SEE) to confirm the mitigation techniques. Finally, a demonstrator ASIC was developed with Frontgrade Gaisler to confirm readiness of the libraries and integration views for making rad-hard components.
The measurements obtained from various test vehicles are used to calibrate SETstriker, a simulation tool that can identify Single Events Transient (SET) vulnerabilities at cell level.

Library design

For digital ASIC designs, the DARE65T platform includes 1.2V standard cell libraries that contain multi-Vt, multi-Lg and hardened cells. A 1.2V Single-port SRAM compiler allows for generation of any memory configuration, and 5 specific 1.2V Dual-port SRAM instances (0.5/1/4/8kx40b, 2kx24b) were designed. The IO offering includes multi-voltage programmable LVCMOS IO, LVDS (800 Mbps), SSTL15 (800 Mbps), SSTL18 IOs (800 Mbps) and a 96-bit DDR3 PHY hard macro block, where all IOs are cold-spare capable for redundant application. In addition, the platform provides several hardened mixed signal IPs: PLL (6.25 MHz–1.2 GHz), Bandgap-based current and voltage reference blocks (IVREF), current-steering digital-to-analog converter (IDAC), and a 1-ksps 10-bit on-chip temperature sensor.

Library test results

In this article we will address the technology components (NMOS, PMOS and BJT transistors, decoupling capacitors, resistors and diodes) and present the library validation results. No TID effects were observed for decoupling capacitors and diodes. For the unsalicided polysilicon resistor, the resistance drift was observed and explained for the first time. For the NMOS, PMOS and BJT transistors, parameters did drift as expected.

The results proved the IP robustness at least to 300 krad(SiO2) and no SEL observed during heavy ion tests up to 74 MeV∙cm2/mg (highest LET tested). The DARE65T platform provides a system designer with the variety of options needed to find the optimal solution from radiation hardness, fault tolerance, performance, area, and power consumption point of view: hardened (DICE-based flip-flops and clock-gating cells, C-elements, majority voters, etc.) and unhardened elements, threshold voltage options, etc.

Besides the standard cell and IP libraries, the platform users can access the SPICE-level SET striker software tool, fully compatible with the standard design flow. The tool allows for finding the sensitive area of the designed block and, in the case of redundant cells, indicating the sensitive pairs. Further layout analysis allows for improving the SEE robustness. For example, the DICE flip-flops use sensitive node spatial separation, and some weak points were found using the SET striker at the design stage. The heavy ion tests proved the robustness of the hardened flip-flops to an LET of at least 15 MeV∙cm2/mg, which is more than 10 times higher than the threshold LET of the previously reported unhardened devices and exceeds the maximum LET level of the high energy proton events.

With this information, the library cell design, and layouts were validated and considered ready for integration in a Demonstrator ASIC to also validate the integration views.

Demonstrator ASIC

Using the digital and mixed signal libraries, Frontgrade Gaisler designed a LEON5FT-based SoC named D65D (DARE65T Demonstrator). The architecture consists mainly of the following functional blocks and characteristics:

• 1x LEON5FT processor core with:
• Integer unit with 8-stage dual-issue pipeline.
• 4x4 KiB instruction and 4x4 KiB data L1 caches connected to a 128-bit multi-layer bus.
• Double-precision IEEE-754 floating point unit.
• Memory Management Unit (MMU).
• 128 KiB L2 cache, 512-bit cache line, 2-ways.
• 96-bit DDR2/3 SDRAM with Reed-Solomon EDAC.
• SpaceWire router with 4 external links.
• High-speed serial link SpaceFibre controller (no on-chip Serializer/Deserializer transceiver).
•x 10/100/1000 Mbit Ethernet interface.
• Other interfaces, such as MIL-STD-1553B (1x), CAN-FD (2x, with CANOpen support), UART (4x), SPI (2x), I2C (2x), GPIOs, FPGA
supervisor (GRSCRUB), SoC bridge, etc.
• Timers and watchdog.
• JTAG and Ethernet debug communication links.
• System frequency of 200 MHz.

Two test hardware setups were developed: one for functional and SEE testing and another for TID testing. A test software suite was also developed to exercise the SoC's main functional blocks.

Demonstrator test results

One heavy ion SEE test campaign and one TID test campaign were executed with the D65D.

The SEE testing was performed at the Radiation Effects Facility (RADEF) of the University of Jyväskylä (JYU), in Finland. The irradiation of three samples was in air using ion cocktails that allowed covering an effective Linear Energy Transfer (LET) range from 0.94 to 94.01 MeV∙cm2/mg at room temperature. The main results obtained were as follows:
• SEL immunity up to an LET of 94.1 MeV∙cm²/mg (tested with elevated temperature - ~100 ºC - and maximum supply voltages).
• SEU results collected with the device operating in dynamic mode in agreement with reference data from the DARE65T library. There is no evidence of error build-up in the D65D.
• Functional results (SEFI and SDC) obtained through the execution of multiple software test cases aimed at exercising the majority of the hardware blocks of the D65D.

The TID testing was performed at ESA’s ESTEC Co-60 facility, located in Noordwijk, The Netherlands. The irradiation of ten samples (five biased, five unbiased, and two reference samples) was performed with a dose rate of 0.426 krad(SiO2)/h from 0 to 100 krad(SiO2) and 2.170 krad(SiO2)/h from 100 to 300 krad(SiO2). No TID-induced failures were observed in any test sample at any test step. Additionally, no evidence of time-dependent effects was observed in any sample after the accelerated ageing test step regardless of the biasing mode. The results obtained reinforce the TID tolerance of 300 krad(SiO2) of the DARE65T library.

The final version of this work will present additional information about the test conditions and detailed results of the two irradiation campaigns (SEE and TID) performed with the D65D component, such as static and dynamic cross-sections obtained from the SEE tests.

Speakers: Lucas Antunes Tambara (Frontgrade Gaisler AB), Dr Marcel van de Burgwal (IMEC)

AMICSA 2025 DARE65T_TV_vdburgwal.pdf

AMICSA 2025 DARE65T_TV_vdburgwal_pres.pdf

12:30 PROMISE, PROgrammable MIxed Signal ASIC Electronics Electrical Characterisation

the results of characterising cell components from the EU SPACE programme Supported PROMISE radiation hard, cell library for space applications

Speaker: Dr Dimitrios Baramillis (ISD)

ADC AMICSA 2025 paper.pdf

ADC AMICSA_2025 presentation.pdf

ADC AMICSA_2025 presentation.pptx

baramilis.amicsa25.pdf

13:00 → 14:30 Lunch

14:30 → 16:00 Exhibitors

Technology Showcase: Industry Solutions for Space-Grade Microelectronics

14:30 Microchip Mixed Signal Solutions for Space

For several decades, Microchip provides one of the industry’s most comprehensive space product portfolio of radiation-hardened and radiation-tolerant solutions that includes high-performance MCUs, MPUs, FPGAs, memories, communication interfaces, frequency and timing solutions, mixed-signal ICs, custom power supplies, diodes, transistors, RF components and more. With product development activities and qualified supply chain in Europe, Microchip France is key contributor to the European space ecosystem delivering European and ESCC qualified solutions.

Use of microcontrollers for space applications is expanding to manage different type of control (sensors, motors, antennas,...) for different kind of cases like satellites, launchers, rover & other robotic equipment. Integration of digital-to-analog converters, analog-to-digital converters, and on-chip non-volatile memory together with a powerful processor core is a the main microcontroller value. This kind of complex but also highly integrated devices is requiring the most advanced mixed signal technology combining digital and analog functions in the same System on Chip.

At AMICSA 2024, Microchip propose to update European space community on space microcontrollers (MCU) solutions developed in France.
SAMRH707 Rad Hard ARM MCU funded by ESA (also name JAGUAR) is now fully QML/ESCC qualified in ceramic but also in plastic package so qualification and radiations results will be shared.
A new Rad Tolerant ARM MCU is going to complete Microchip ARM RT microcontrollers portfolio with the announcement of SAMD21J17RT bringing Cortex M0+ with analog capabilities to the space market. More detailed presentation of this new mixed signal microcontroller is proposed for AMICSA 2024.

Around microcontrollers, Microchip will update on connectivity mixed signal devices under development. With new Quad Port Ethernet PHY VSC8574RT, Microchip is going to complete Ethernet space qualified offering with a SGMII/QSGMII interface to connect to any copper and fiber Ethernet physical media. Update on CAN FD transceiver for space activity at Microchip will be also proposed. Those projects are supported by CNES funding.

A short introduction about new on going development at Microchip with the European ATMX150RHA space qualified mixed signal technology will be also provided. This technology is still available for European space industry with prototyping capabilities supported by space agencies ESA and CNES.

As a key contributor to the mixed signal European solutions, Microchip will be really please to update space European community on all those topics during AMISCA 2024 in Germany.

Speaker: Simon Dumortier

1_Microchip-Mixed-Signal-Solutions-for-Space-AMICSA-2025.pptx

14:45 ASICS ORGANIC PACKAGING

Integrated Circuits rule the world of electronics including space electronics. Electronic components are available either in discrete or integrated form. The discrete form is reserved for standalone components only, like a transistor, diode, resistor, capacitor, or inductor. All sorts of circuits – analog, digital and mixed-signal, and all types of components – passive or active can be integrated into an IC.
As the technology advances towards ultra-deep in submicron generations, density and performance of individual chips are continually enhanced. Unfortunately, today, not all of these merits can be translated into system level due to the problem of electronic package, which has presented a bottleneck for increasing system speed, reducing power, and shrinking system size.
In addition, the package itself and on-board interconnects have much larger dimensions than that of the on-chips. They are hence large loads of off-chip drivers. Besides the higher power consumption and larger chip size for these off-chip drivers, system performance is severely degraded. Consequently, preservation of signal integrity and timing becomes a difficult challenge as signals move from chip to chip within the system. It is hence necessary to minimize impedance discontinuities at chip-to-package and package-to-board interconnection junctions and reduce cross-talk noise between adjacent lines.
The packaging of an integrated circuit is as important as the integrated circuit within, and mainly serves three purposes which are:
• protection of the semiconductor circuit from physical impairment or damage,
• protection of the circuit from corrosion,
• and finally and most important, it decides how electrical contacts are laid out from the semiconductor device over a PCB.
The packaging of an IC gets really important when it has to be used on a PCB for space applications. Complementary to ceramic packaging used for legacy, IC’s are now being used for new space applications in plastic packages using surface-mount technologies.
SERMA MICROELECTRONICS, is pleased to announce a One-stop shop for design and manufacturing of MSL3 BGA packaging service with full compliance to JEDEC & ESCC standards, and available to the entire European & World Wide Space domain.
We aim to develop solutions which will enable new encapsulation method for ASICS with:
• Ever-greater levels of integration (SiP, embedded components, heterogeneity, etc.)
• Customized solutions: in terms of technology (plastic, ceramic, power, RF packaging) and volume (prototypes and production up to a few thousand ku)
• Proven REX and reliability (35 years' experience, ESCC9030 qualifier)
• New possibilities offered by the addition of metallization levels on chips (UBM, RDL, bumping, etc.)

Speaker: Lionel Bouyssi (Serma)

2_AMICSA 2025 - Serma Microelectronics.pptx

ABSTRACT FOR ASICS ENCAPSULATION.pdf

15:00 Advancements in RF Test and measurement technology

Exhibitor Presentation

Speaker: Mr Ricardo Freitas (Rohde & Schwarz)

ROHDE & SCHWARZ_AMICSA2025_Advancements in RF Test and Measurement Technology.pptx

15:15 IMEC

Exhibitor Presentation

Speaker: Mr Geert Thys (imec)

4_imec-AMICSA-2025-Monday.pdf

15:30 Alter

Exhibitor Presentation

Speaker: Thibaut Fabien (Alter)

Alter Technology - AMICSA 2025.pdf

15:45 PETsys

Exhibitor Presentation

Speaker: Miguel Silveira (PetSYS)

6_Petsys_AMICSA2025_MSilveira.pdf

16:00 → 16:30 Coffee

16:30 → 17:30 Phase Locked Loop

Radiation-Tolerant PLL Design for Frequency Stability in Space Systems

16:30 Jitter Measurement Results of DARE22 Phase-Locked Loop

The DARE22G Phase-Locked Loop (PLL) has been designed in a 22nm Fully Depleted Silicon On Insulator (FD-SOI). It is required to be not only a radiation-hardened, but also low jitter PLL, with a target period jitter of less than 1ps for a 3GHz output frequency. As the application of the DARE22G PLL is in a digital system, period jitter is selected as a requirement in this design, instead of absolute jitter and cycle-to-cycle jitter. In the DARE22G PLL, the maximum output frequency of the loop itself - composed of a Voltage-Controlled Oscillator (VCO) based on a ring oscillator, a programmable Charge-Pump (CP) synchronized with a loop divider, a Phase Frequency Detector (PFD), Feedback Divider (FDIV) and a 2nd order Low Pass Filter (LPF) - is 3GHz, and two frequency dividers are connected to the output of the loop in series. They are called ODIV1 and ODIV2. If the division factors of ODIV1 and ODIV2 are set to 1, the DARE22G PLL output frequency is 3GHz.

The test structure for the jitter measurement is simply one test buffer connected to the output of the DARE22G PLL. The test buffer is an inverter with high driving strength and decoupling capacitors to suppress supply noise. Since the high inductance of the bond wires easily attenuates and corrupts high frequency signals, it is essential to minimize the inductance of the bond wires. For this purpose, firstly, three pads are connected to the test buffer output to implement three bond wires in parallel. Secondly, the bond wires on the silicon chip are directly landed on the test board without a package.

In the theory of PLL design, the input clock frequency and the division factor of the output dividers (ODIV1 and ODIV2) must have no impact on the period jitter (rms value) of the PLL output clocks. We measured the period jitter for 30 configurations, which are combinations of the input clock, FDIV, ODIV1, and ODIV2, to confirm the theory. Configuration A-1 has an input clock of 23.4375MHz, a division factor of FDIV=128, and division factors of ODIV1=1, and ODIV2=1, 2, 4, 8, 16, 32, 64, 128. The input clock of 23.4375MHz is the minimum required for the DARE22G PLL to create 3GHz output clock. In Configuration A-2, the input clock frequency and FDIV’s division factor are the same as in Configuration A-1, with the only difference being the division factors ODIV1=2 and ODIV2=1, 2, 4, 8, 16, 32, 64. Configuration B-1 has an input clock of 100MHz, a division factor of the FDIV=30, and the same division factor for the output dividers (ODIV1 and ODIV2) as Configuration A-1. The input clock of 100MHz is the maximum input clock that the DARE22G PLL can use to create a 3GHz output clock. Configuration B-2 has the same input clock frequency and the FDIV division factor as Configuration B-1, with division factors for the output dividers (ODIV1 and ODIV2) the same as Configuration A-2. These configurations are controlled by a Serial Peripheral Interface (SPI) implemented in the test vehicle.

The test instruments used include the Keysight N6704B power supply, R&S SMA100B signal generator, R&S RTP084 high performance oscilloscope (Bandwidth 16GHz), and Digilent Digital Discovery pattern generator as a SPI controller.

During the measurement, the DARE22G PLL operated with a 0.8V nominal supply voltage at room temperature. As a result, it has been confirmed that the input clock frequency and the division factor of the output dividers (ODIV1 and ODIV2) have no impact on the period jitter (rms value) of the PLL output clocks, as the measured period jitter shows consistency for all configurations. In conclusion, the DARE22G PLL’s period jitter (rms value) is 0.6 picosecond for a 3GHz output clock frequency.

Speaker: SinNyoung Kim (imec)

Jitter_Measurement_DARE22G_PLL_AMICSA_2025.pdf

Jitter_Measurement_Results_of_DARE22G_PLL.pptx

17:00 ITAR-free Multi-Output Low Phase Noise Radiation Hardened by Design PLL

A fully integrated radiation-hardened all-digital frequency synthesizer, designed in a commercial CMOS technology, is presented in this paper. Radiation hardness by design is implemented in all analog and digital blocks and throughout the chip architecture. The simulated normalized phase noise is at -230 dBc/Hz, hence outperforms its measured prototype of -210 dBc/Hz. The synthesizer can work with an on-chip crystal oscillator and supports external references between 10-100 MHz. The chip supports 4 differential outputs at various signaling standards up to 1 GHz and 2 differential RF drivers up to 5 GHz. The radiation tolerance was validated on a prototype up to a total-ionizing-dose (TID) level of 100 krad(Si) and a single-event latch-up (SEL) / single-event upset (SEU) level of 62.5 MeV·cm²/mg.

Speaker: Dr Maarten Strackx (Magics Technologies)

Magics_ADPLL_AMICSA2024_abstract.pdf

Magics_ADPLL_AMICSA2025_finalpaper.pdf

Magics_ADPLL_AMICSA2025_presentation.pdf

Tuesday 17 June

09:00 → 09:45 Keynote

Pushing the Frontiers of Microelectronics for Space: Challenges, Trends, and Vision

09:00 RF-sampling ADCs for next-generation wireless applications

Speaker: Dr Jorge Lagos (IMEC)

2025_AMICSA25_JL__deliverable.pdf

09:45 → 10:15 Image Readout

Advanced Image Readout Circuits for High-Reliability Sensing in Orbit

09:45 Development of an Infrared FPA Readout System with the NIRCA ASIC

This paper describes the development of a focal plane array (FPA) readout system based on the NIRCA application specific integrated circuit (ASIC). The system aims to reduce the size, weight, power, and cost of IR image sensor systems. We have developed NIRCA and board-level electronics with NIRCA that allows users to connect FPAs and acquire data via Camera Link (CL) to their computers. The board-level electronics allows one to design instruments with NIRCA packaged in 208-pin CQFP, which currently is being qualified for flight. We describe the functionality and performance of NIRCA with the board-level electronic system. Using a function generator connected to all 16 video inputs we demonstrate that the system can read out with 16-bit resolution and transmit mega-pixel frame size at a frame rate of up to 183fps (frames per second).

Speaker: Dirk Meier (Integrated Detector Electronics AS)

Abstract-AMICSA2025_IDEAS_NIRCA.pdf

IDEAS-at-AMICSA2025-IRFPA-Readout-NIRCA-MkII-ASIC_2025-06-17.pptx

10:15 → 11:00 Coffee

11:00 → 13:00 Data Converters

High-Integrity Data Converters: Bridging Analog and Digital in Radiation-Prone Missions

11:00 Low Power Radiation Hardened by Design TDC with 8 ps Single-Shot Precision

A rad-hard by design Time-to-Digital Converter is presented with a single-shot precision of 8 ps and a zero dead zone measurement range of 0 ps up to 3s. The analog and digital building blocks and the overall chip architecture are developed for radiation performance, to support time of flight and time tagging applications in space.

Speaker: Dr Bjorn Van Bockel (Magics Technologies)

Abstract.pdf

full paper.pdf

Presentation.pdf

11:30 A High-performance TID- and SEE-Tolerant ADC in 65 nm for Space Applications

In space-related projects, radiation effects such as Total Ionizing Dose (TID) effects and Single Event Effects (SEEs) are the main threat to the microelectronic conponents. ADCs, which are the crucial components of the telecommunication chain, are also facing these challenges. Radiation hardening is mandatory for the assurance of function and performance for ADC, which usually brings penalties to power efficiency. This paper presents a high-performance pipelined-SAR ADC, which is designed by revealing and balancing the tradeoffs between power efficiency and radiation tolerance, achieving 80MS/s and 70.79-dB SNDR with high conversion efficiency and radiation tolerance to TID effects and SEEs. TID irradiation tests confirm that the ADC remains unaffected up to 500 krad(Si), displaying robust resilience. Notably, the ADC exhibits a limited SEE-sensitive region and swift recovery even in the occurrence of SEE events. With a total power consumption of 13.8 mW, the prototype ADC establishes a state-of-the-art Walden Figure of Merit of 60.7 fJ/conv step, yielding a comparable efficiency compared to the non-radiation-tolerant ADCs with similar specifications.

Speaker: Zheyi Li (IMEC)

2_AMICSA2025_ADC_V2.pptx

Abstract_HighPerformanceADCforSpaceApp_Submit.docx

FullPaper_HighPerformanceADCforSpaceApp_Submit.pdf

12:00 A 33 GHz Bandwidth 12.8 GSps 10-bit ADC for Space and Ground Applications Enabling Direct Ka-band Conversion

This paper presents a compact, high-speed 10-bit wideband data converter for direct conversion of the microwave spectrum up to 40 GHz (Ka-band). With a 33 GHz input bandwidth, it supports RF direct sampling at 12.8 GSps with only 2.5W power consumption, eliminating the need for external mixers and simplifying system design. NPR performance has been measured up to 40 GHz, making it ideal for aerospace, telecommunications, and defense. The integrated digital down conversion (DDC) supports advanced features like frequency hopping and beamforming, making it perfect for applications with strict power, size, and performance needs, enabling software-defined mmWave radio for future-proof architecture.

Speaker: Mrs Heline Barneoud (Teledyne e2v)

AMICSA 2025 Abstract.pdf

AMICSA 2025 Final paper.pdf

ESA-Te2v-AMICSA- AS940- 17JUNE2025.pdf

12:30 Design and Test of a Radiation-Hardened 14-bit 80 MS/s SAR-Assisted Pipeline-ADC in 28-nm Bulk-CMOS

This paper presents the design, implementation, and experimental validation of a 14-bit 80 MS/s calibration-free radiation-hardened pipeline analog-to-digital converter (ADC) realized in 28-nm bulk-CMOS technology. The escalating demand for high-performance ADCs in radiation-rich environments necessitates robust designs capable of withstanding ionizing radiation-induced errors without compromising performance. Traditional radiation-hardened ADC solutions often entail complex calibration procedures, leading to increased power dissipation and design complexity. In contrast, our proposed ADC architecture leverages the inherent advantages of the pipeline topology, coupled with innovative circuit techniques, to achieve resilience to radiation-induced errors without the need for calibration. By eliminating calibration overhead, the proposed design minimizes energy consumption while maintaining high precision and throughput. The paper outlines the architectural principles, circuit implementations, and radiation-hardening techniques employed in the ADC design. The performance of the ADC was experimentally characterized for normal operation and for a TID (Total Ionizing Dose) of 100 krad(Si). The circuit was also tested for SEE (Single Event Effects), covering SEU (Single Event Upset), SEL (Single Event Latchup) and SET (Single Event Transient) under heavy ions radiation. This calibration-free pipeline ADC represents a significant advancement in radiation-hardened ADC design, offering a compelling solution for applications in space missions, nuclear facilities, and other radiation-prone environments where reliability and energy efficiency are paramount.

Speakers: Dr Fábio Passos (Instituto Superior Técnico), Dr Hugo Serra (UNINOVA), Dr João Goes (UNINOVA)

AMICSA_2025_ADC1480_FINAL_extended.pdf

AMICSA_2025_presentation_vhs.pdf

13:00 → 14:30 Lunch

14:30 → 16:00 Power Circuits

Robust Power Management Circuits for Harsh Space Environments

14:30 CONAN – An Electronic Circuit Breaker for Next Generation PCDU

CONAN IC has been designed in the framework of ARTES ESA program by a consortium composed of Airbus Defence and Space, which has specified the requirement for this electronic circuit breaker, and Weeroc which has designed the CONAN IC. Telecom Satellite Power Control and Distribution Units (PCDUs) in particular and most satellite PCDUs in general still use fuses as circuit breaker. Having a programmable electronic circuit breaker controller device featuring double isolation, redundancy, telemetry and latch-up current limitation will be a game changer for PCDUs circuit breaking. CONAN is a dual power P-channel MOSFET controller IC (nominal and redundant) designed in XFAB XT018 technology. It embeds all these features over a 20 V to 136 V voltage span and a 0.5 A to 12.5 A current limitation span. CONAN features a nominal and redundant space serial bus communication line allowing the TM/TC of 254 CONAN on the same bus line. CONAN embeds 8-heater drivers and 8-heater status on top of the circuit breaking capability. CONAN complete features and architecture will be presented in this paper along with simulation and measurement results.
This work was funded through the ARTES 4.0 Core Competitiveness programme by the European Space Agency (ESA) Contract No. 4000134556.

Speaker: Julien FLEURY (WEEROC)

AMICSA 2024 - CONAN abstract.pdf

AMICSA25 - Conan - a 130V electronic circuit-breaker and latch-up current limiter controller.pdf

15:00 A Rad-Hard Quad Power Switch with Fuse-like Fault Shedding Characteristic

Abstract

In this paper we present the design and applications of a new rad-hard quad power switch that emulates fuse load shedding characteristics (i.e. shorter load shedding time for higher currents with a slow shedding time close to the load rating current). The fuse type load shedding time, also called $i^2t$ type characteristic, corresponds to a fixed amount of dissipated energy and is a natural fit for the physics of protecting the switch element. We will show how this characteristic type is implemented in silicon, how we managed the protection of the switch element and some test results for regular as well as radiation environment operation. Finally, we demonstrate application aspects including a fault tolerant redundant switch implemented using this new circuit.

Introduction

In power distribution for space applications there is a need to protect all types of loads. Besides regular loads that can be efficiently protected by LCL and RLCL conforming to ESA standards (see e.g. [1]), there are some subsystems that do have large and long inrush currents. Examples of these are relay boards or actuator circuits that start on a heavy load. If one uses a regular (fixed current and fixed trip time) LCL, the trip current needs to be set at a level corresponding to a derating of the peak load inrush current or the trip time needs to be larger than the inrush time. This protection will not be effective if normal operating conditions are at e.g. 10x lower currents and fault currents are lower than the inrush current. If one sets the trip current level lower than the inrush current, then the trip time of the [R]LCL needs to exceed the inrush time. This kind of protection is not effective because, if there is a massive load fault, the energy dissipated in the load and switch is proportional to the increased trip time and could be large enough to exceed the protection devices ratings. So, there is a need to protect loads with trip times that depend on the (fault) current in the load.

Fuse-type Load Shedding Characteristic

Traditionally space qualified fuses and relays were used to protect loads in power distribution across satellite subsystems because of these being relatively inexpensive, small, and light. As described in the introduction, the application of standard (constant trip time) electronic RLCLs cannot be optimal for some subsystems especially those that have substantial inrush current and time and those that could be susceptible to conductor fusing (e.g. electrical motors).

The fuse type load shedding is characterized by the fact that the trip time is inversely proportional to the square of the fault current.
$$ T_{trip} = K/(I_{fault}^2) \ \ \ \ \ \ (1) $$ Where $K$ is a constant depending primarily on the fuse construction and temperature, and $I_{fault}$ is the extra current above the rated current. If the current is not constant the trip time is defined by the implicit equation: $$ ∫_0^{t_{trip}}i_{fault}^2 (t)dt = K \ \ \ \ \ \ (2) $$ If the load has an equivalent series resistive component, then the actual total energy dissipated due to the fault current in the load is also constant: $$ W_{load\ fault}=∫_0^{t_{trip}}R_{load} i_{fault}^2 (t)dt = K R_{load} = constant\ \ \ \ \ \ (3) $$ This will yield a maximum energy dissipated in the conductor or windings of the load. Examples of these kinds of loads are loads that have resistive (and inductive) are heaters, relays and motor drives. Efficient protection of these types of loads can be done only using a fuse-like trip characteristic. An Integrated RLCL with Fuse-type Characteristic ---------------------------------------------------- A fully integrated fuse-type characteristic RLCL for space applications was designed and implemented in a 60V space qualified monolithic technology (see [2]). The circuit consists of four isolated channels with differential input on/off control and fault/state signaling. The trip characteristic of the device is similar to existing fuse characteristics within a typical operating range. The device comes in two rated currents 1.2A and 2.5A. Additionally, each channel has a comprehensive set of protections to guarantee protection of both load and protecting device (see Figure 1 for a high-level block diagram) and implements a turn on / turn off slew rate control. A current limit set at around 10A as well as a fast heavy load secondary fault response is implemented to avoid internal device damage. A maximum junction temperature protection set at more than 150°C with a hysteresis turns off the device if all other protections fail. The main $i^2t$ protection (see figure 2) calculates the integral from equation 2 using a current to voltage converter (the current sense block) followed by a squarer and a voltage-controlled oscillator (VCO). The trip limit (constant $K$ in eq. 1 or 2) is set as a fixed number of periods ($N=4096$) of the VCO output. The trip condition can be written as follows: $$ V_{i_{sns} } = a_1 i_{sns};\ \ f_{VCO}=a_2 (V_{i_{sns}} -V_{trip} )^2;\ \ t_{trip}=N/f_{vco}\ \ \ \ \ \ (4) $$ $$ t_{trip}=\frac{N}{a_2 a_1^2 i_{fault}^2} $$ therefore $$ K=\frac{N}{a_2 a_1^2}\ \ \ \ \ \ (5) $$ The rated current is controlled by the $V_{trip}$ offset and $K$ is controlled by changing the VCO gain $a_2$. After a fault trip, the channel restart is timed by a timer set to about ten seconds giving enough time for the load and power MOSFET to cool down. The device also implements a maximum number of retries set to 4096. This avoids unnecessary retries if restarts will not “burn” the load fault condition. The secondary protection is implemented as a limit for maximum instantaneous power dissipated in the sense resistor and nearby power MOSFET. This is realized as a limit comparator for the difference of junction temperatures read in the power device vs. the rest of the die. This temperature difference is developed on the die thermal resistance and is proportional to the power dissipated in the resistor and MOSFET. This sets a limit for the resistor and MOSFET safe operating region. Incidentally, if the max power (temperature difference) protection corresponds to an $i^2t$ characteristic that triggers at high levels of power. This is because at high levels of power the energy dispensed does not have time to propagate through the thermal resistance and the local junction temperature increase will be proportional to the power ($i^2r$) and to the fault time. Assuming the energy propagated through the thermal resistance to the rest of the die is negligible with respect to the flow of energy (power) dissipated in the resistor + MOSFET is predominantly a resistor we can write the following equations: $$ T_1≈T_0+ci^2 r_{eq} t;\ \ T_2 ≈ T_0\ \ \ \ \ \ (6) $$ $$ ∆T_{lim} = c\ i^2 r_{eq} t_{fault} = k_1 i^2 t_{fault}\ \ \ \ \ \ (7) $$ Setting the temperature difference limit dictates the trip time. The final paper will describe in more detail the interaction and codesign of both moderate and heavy load protection parameters. Applications ------------ The typical application for this circuit is to substitute the fuse and relay trays in classic satellite power distribution (see figure 3). To compare the protection performance of LX7714 to a classically implemented RLCL we sized two applications similar to the condition described in the introduction and compared the measured data from LX7714 to calculated data representing the classical RLCL. Figure 4 shows the two cases from the perspective of the RLCL MOSFET and from the perspective of the load circuit dissipated energy. Both applications were sized similarly at moderate overload of 150%. One can see a medium advantage for LX7714 on medium overload condition and an advantage of 4 orders of magnitude for LX7714 in the heavy overload both for the RLCL MOSFET and for the load circuit. The final paper will describe the implementation and measurement results of a redundant fault tolerant RLCL using LX7714. Performance in a radiation environment will also be shown as more data will be available. Conclusions and Future Work --------------------------- An integrated implementation for an RLCL with fuse-like load shedding characteristics was presented. Some of the advantages of the protection scheme reside in the fact that this characteristic is a natural fit with the safe operating area for a pass transistor and the fact that is a better solution compared to traditional LCL/RLCL for protecting loads that have large and/or long in-rush currents at start-up or when they are enabled. Applications with bidirectional isolation between line and load will also be developed. Bibliography ------------ [1] European Cooperation for Space Standardisation, ECSS-E-ST-20-20C, Space engineering - Electrical design and interface requirements for power supply, 15 April 2016 [2] “Quad 46V, 2.5A/1.25A RLCL Power Switches for Space”, LX7714 preliminary datasheet, Microchip Technology Inc., 2023 https://www.microchip.com/en-us/product/lx7714 Figures ------- **Figure 1**: Functional diagram for one of the four LX7714 channels   **Figure 2**: Detailed functional diagram of LX7714 (one of four channels). **Figure 3**: Typical system application. **Figure 4**: Comparing the dissipated fault energy before trip time for the MOSFET switch and for the load circuit between the constant time fault case and LX7714 implementing i2t characteristic. Vertical axis: Energy in Joules, horizontal axis load as a percentage of the rated load ($G_{rated} = I_{rated} / V_{line}$).

Speaker: Dr Sorin Spanoche

Abstract_AMICSA_2024_sspanoche.pdf

AMICSA2025_Spanoche_Sorin_slides_final.pdf

AMICSA_2025_spanoche_sorin_final.pdf

15:30 GaN half-bridge integrated circuits for power converters

This talk aims at presenting the results from several programs

SloGaN VLAIO project (Flemish regional funding)
GAN-IC4S ESA GTSP program
EleGaNt European Commission H2020 Space work program

GaN Half-bridges were developed and tested. The aim was to achieve integration of high voltage & high current transistors with low voltage control & gate drive devices.

Speakers: Mr Marc Fossion (Thales Alenia Space Belgium), Dr Mike Wens (MinDCet NV)

ELEGANT-TASB-PPT-0052-01-AMICSA2025_GaN-IC-Results.pdf

16:00 → 16:30 Coffee

16:30 → 18:00 Power Circuits

Robust Power Management Circuits for Harsh Space Environments

16:30 A Scalable COntroller for Power Sources (SCOPS)

The PROMISE Design Standard and Library is currently being used (and expanded) to develop a very high efficiency, low voltage, high current DC-DC power converter, based on a novel architecture of control, which allows it to be flexible and reconfigurable as a function of application and fault tolerance requirements. This Scalable power source controller IC ( SCOPS) is targeted for use in space and satellite applications which require a robust power supply that can deliver the consistent low voltage and high current that is required to drive advanced electronic technologies, all of which are tending towards low voltage operation but which also exhibit very high currents as a function of the numbers of transistors being deployed.

Speaker: Prof. Marc COUSINEAU (LAPLACE, Université de Toulouse, CNRS, INPT, UPS, Toulouse, France)

1_AMICSA - Marc Cousineau - SCOPS V2.pptx

AMICSA25.SCOPS.2.pdf

17:00 GaN ready single chip DC-DC controller for space applications

Thales Alenia Space has partnered with MinDCet (IC design house) in an ESA program for the development of a single chip dc-dc controller. The IC design was done on SOI and high voltage process.

Controller run2, was developed & tapped-out in development under an ESA GSTP program. Formal qualification for Space is reaching its end. The component Plastic BGA has now been successfully included in several dc-dc converter applications.

Early samples of the component will now become available for any European dc-dc designers.
MinDCet will perform component distribution and customer support.

Speaker: Mr Marc Fossion (Thales Alenia Space Belgium)

HSC-RUN2-TASB-PPT-0169-02-GaN-ready-Controller.pdf

17:30 LLC with Flyback DC-DC Converter for the Supply of Low Voltage and High Current in Space Applications

This paper describes work on the characterisation of a Low voltage \high current DC DC converter for space applications

Speaker: Dr Patrick Dubus (Powerology and ISD Integrated Systems)

3_AMICSA_2025_CV_LVHI_1v1.pptx

AMICSA25f.pdf

Wednesday 18 June

09:30 → 10:15 Keynote

Pushing the Frontiers of Microelectronics for Space: Challenges, Trends, and Vision

09:30 Radhard electronics systems of the new CMS Timing Detector at CERN's Large Hadron Collider

Speaker: Dr Joao Varela (CERN)

Radhard electronics of CMS Timing Detector- AMICSA'25 .pdf

10:15 → 11:00 Coffee

11:00 → 12:30 Radiation Testing

Radiation Testing Strategies: From Ground-Based Campaigns to Flight Correlation

11:00 Eliminating Measured Radiation Effects to go for FM-Level Mixed Signal Design

After nearly a decade of prototyping and designing on XH180 at TESAT, our first design RUCA has finally reached FM-Level and is ready for launch. The RUCA is a mixed signal ASIC, build to bias external RF-components. For this purpose, DACs, ADCs, on-chip power supply and biasing, regulation loops and a huge digital part have been implemented. All these functionalities showed sufficient performance in our lab experiments. Before qualification could start however, the last step was to eliminate issues, which had been discovered during radiation tests of the last prototype device. These effects included inhibited operation due to drifts during total dose tests, single even transients on analog outputs and device destruction under high energy Xenon irradiation with 62.5 MeV/(mg/cm²). All destructive effects have been successfully eliminated and transients have been mitigated down to an acceptable level.

Here, we will describe the journey from the prototype to the FM considering radiation. This includes radiation test setups, tests carried out and their outcomes, methods of analysis and finally the solutions to eliminate destructive effects and to mitigate nondestructive effects.

For TID-Testing, we have developed a very flexible setup consisting of several small boards, which can be arranged in equivalent distances to the radiation source and a test system for screening the devices. Screening is done automatically with minimum user intervention and can be done by none expert users. The same setup can be used for burn in and life tests. Data of each run has been evaluated directly and drifts have been calculated. As for all our tests, a python test framework is used. During prototype testing, a single circuit failed earlier than expected, so the complete device could not stand high doses. Further irradiation of the prototypes was possible, however.

After the tests, we developed an analysis method using a circuit simulator. We added voltage sources in series with the gates of each single transistor and looked for the devices, which failed first or had most influence on the output. This way, the complete circuit failure could be traced to a single MOS device, whose channel did not close anymore. The easiest and working solution was to use the affected high voltage device for protection only and to work with a low voltage device for functionality.

For single event testing, a completely different approach is necessary, as all data has to be collected very fast during a very short period of irradiation. For this purpose, we developed an FPGA-based measurement platform. The setup can on the one hand observe several observables in parallel and count the crossing of adjustable thresholds. On the other hand, some observables can be switched onto coaxial outputs for measurements outside the chamber with the oscilloscope. This way single event rates can be measured while the exact figures of transients can be observed, too. A very fast latch up protection compares the current flowing through a shunt resistor with an adjustable threshold and cuts off the device it is crossed.

We had three major outcomes of the first test: One circuit part showed a single event functional interrupt requiring a power cycle of the device. As this circuit was not necessary for the FM functionality, it has been completely removed. Moreover, the single event transient behavior of some analog outputs has been worse than expected. It has been possible to improve those outputs. The worst outcome however has been a destructive behavior at Xenon (62.5 {MeV/(mg/cm²)}). A massive raise in current has been observed triggering our latch up protection. This current remained static even after a power cycle and seemed to be additive. There could be several of those events.

Several test runs and analysis methods could track the failure to a single circuit in the device. Interestingly it is most probably no latch up, but a gate or diffusion rapture. However, the high current of a latch up might have caused a destruction leading to a high current, so it cannot be proven if it was a latch up, or a direct destruction. The finally easy and secure solution was to remove the bad circuit from the device, as it has not been necessary for operation.

After solving all issues of the RUCA prototypes, it has been possible to finally produce radiation hard RUCA FM-devices.

Speaker: Prof. Sebastian Millner (Technische Hochschule Nürnberg Georg Simon Ohm)

AMICSApaper2025_Millner.pdf

Talk

11:30 Test System for the Experimental Evaluation of a Low-power High-Performance four-channel ADC for Space Applications

Summary
This paper presents the test system developed to evaluate the static and the dynamic parameters of a prototype low-power high-performance four-channel Analog-to-Digital-Converter (QUAD-ADC) during the Total Ionization Dose (TID) and its integration into a Single Event Effects (SEE) test platform developed for the SEE characterization. The DUT (Device Under Test) is a Pipeline ADC of 80MHz maximum throughput rate designed specifically for science instruments in satellite applications. Each channel fully supports parallel low-voltage single-ended CMOS digital interface.
Content
Analogue-to-Digital Converters (ADCs) are key elements at any mixed-signal system as they are the link between the analogue and digital worlds. As devices that are always required, a custom-design for space applications is highly demanded, since the need for superior performance is combined with the need of radiation robustness. Space asks for at a state-of-the-art performance along with radiation hardened technology.
This paper introduces the work carried out for the performance evaluation [1] of a prototype low-power high-performance four-channel 80MSps Analog-to-Digital-Converter (QUAD-ADC) under the Total Ionization Dose (TID) test [2]. The component was irradiated using a Cobalt60 source, with a dose rate of 210 rad(Si)/h and up to 100krad cumulative dose. Five samples were all pin grounded and five samples were biasing in a static configuration. The paper also presents the work developed to perform the SEE characterization [3] of the QUAD-ADC, with the integration of the performance evaluation test system into the SEE test platform [4].
The QUAD-ADC is a Pipeline ADC with an 80MHz of maximum throughput rate. It supports low-power high-speed applications using a low-voltage (1.8V) fully parallel single-ended digital output interface. The converter operates with a 1.8V single external power supply and has a fully differential 2Vpp input range. The ADC includes internal regulators that generate all the internal biases required by the component, with output pins providing the Common Mode and Reference voltages internally derived.
Regarding the test bench setup, it includes the Applicos ATX7006 Automatic Test Equipment (ATE) as input signal generator: its AWG16 module is a 16-bit arbitrary waveform generator up to 200MSps with an output impedance of 50Ohms, high linearity, and with the possibility of signal path filtering. The input signal generation is fully synchronised with the ADC sampling rate by means of an external low jitter clock. The synchronisation has been managed using a very low jitter commercial clock distribution system specially designed to characterise ADCs, driven to synchronise the whole measurement system: signal generation, ADC sampling and data capture [5]. The data acquisition system is the XEM7350 FPGA integration module. The measurement PCB was custom-designed to meet the requirements for the characterisation of the QUAD-ADC: high configuration versatility, minimisation of parasitic elements, careful routing especially on the clock and data lines, decoupling... while maintaining a great adaptability to our SEE platform.
The paper will include an introduction, a first section describing the main setup and the PCBs-Capture system, a second section focused on the system radiation test and finally the conclusions and future work.

Speaker: Manuel Morales

Abstract_AMICSA2025_ALTER_Final.pdf

ALTER_FullPaper_AMICSA2025.pdf

AMICSA 2025_ATN Quad ADC presentation v2.pptx

12:00 Radiation tolerance of the TOFHIR2 chip for the CMS/CERN timing detector

The CMS detector is set to be upgraded for the HL-LHC proton collider at CERN with the addition of a MIP Timing Detector (MTD). The MTD will feature barrel and endcap timing layers, BTL and ETL, to enable precise timing measurements of charged particles. The BTL sensors utilize LYSO:Ce scintillation crystals coupled with SiPMs and TOFHIR2 ASICs for front-end readout. Over the HL-LHC's lifetime, the system is expected to achieve a timing resolution of 30-60 ps for MIP signals at a rate of 2.5 Mhit/s per channel. During its operation, the detector is exposed to a large flux of particles. In consequence, the TOFHIR2 chip must be resistant to the expected total ionization dose TID (29 kGray) and to the integrated particle fluence (2×1014 neq/cm2) in the BTL.

In this paper, we present an overview of the TOFHIR2 requirements and design, and of the measurements performed with TOFHIR2 ASICs with emphasis on the radiation resistance. The measurements of TOFHIR2 associated to sensor modules were performed in different test setups using internal test pulses or blue and UV laser pulses emulating the signals expected in the experiment. Extensive radiation tests, including x-rays and heavy ions, confirmed that TOFHIR2 remains unaffected by the radiation environment throughout the experiment's lifetime.

Speaker: Dr Edgar Albuquerque (PETsys Electronics)

3_AMICXA 2025 apresentação.pdf

AMICSA 2025 paper_PETSYS_final.pdf

12:30 → 13:00 AMICSA: Conclusion

Introduction and Welcome

12:30 Farewell

Speakers: Boris Glass (ESA), João Goes (UNINOVA)

amicsa_farewell_2025_bg.pptx