Efficiently Escaping Low-Level Design in Digital Microelectronics by Wise Auto-Coding of HDLs from High-Level Models

16 Oct 2025, 12:10
20m
Salle 1+2

Salle 1+2

Presentation Validation & verification, testing, qualification, simulation, modelling of complex systems AI Acceleration on FPGAs and HLS

Description

Digital microelectronics for space applications have traditionally been developed at the Register Transfer Level (RTL) through manual process using Hardware Description Languages (HDLs). While this approach has served as a one-size-fits-all solution, recent challenges such as increasing system complexity and reduced times-to-market have motivated the exploration of alternative methods.

This paper focuses on the auto-coding of reliable HDL from high-level models of digital microelectronics, addressing key questions like why, how, and in which space applications engineers are adopting auto-coding tools. Additionally, the paper also provides an overview of the ongoing production of the Handbook for Auto-Coding of HDLs for Space FPGAs, highlighting its main insights and implications for the field.

Author

Mr Alberto Urbón Aguado (ESA - ESTEC - TEC-EDM)

Presentation materials