Speaker
Mr
Gerard Rauwerda
(RECORE Systems B.V.)
Description
The XentiumDARE ASIC is a proof-of-concept design for a radiation-hardened, fault-tolerant multi-DSP system-on-chip with various subsystems to build a powerful digital signal processing system with high data throughput for on-board payload data processing. The main reconfigurable building blocks for creating a multi-core DSP SoC (ie. Xentium DSP, Network-on-Chip and NoC interfaces) have been prototyped in radiation-hardened CMOS using IMEC DARE180 technology.
Originating from the Massively Parallel Processor Breadboarding (MPPB) design, we improved the main reconfigurable building blocks with error correction and detection techniques.
Payload processing software examples have been prototyped on the rad.-hard XentiumDARE ASIC, using the Xentium software development tools which includes a C-compiler, (multi-core) instruction-set simulator, and floating-point emulation libraries.
The Xentium DSP and Network-on-Chip technology are being integrated in future payload processing systems. Based on MPPB and XentiumDARE evaluations we are improving the IP designs according to the users' needs. We will also talk about envisioned feature updates for e.g. the Scalable Sensor Data Processor.
