Speaker
Dr
Seong-Mo Moon
(Electronics and Telecommunications Research Institute (ETRI))
Description
The COMS payloads, up and down link frequency and the bandwidth are all fixed during the lifetime of the satellite. But increasing satellite lifetimes of more than 15 years, the ability to adapt the payload to new scenarios such as flexibility would be highly advantageous. An agile-tunable Local Oscillator (LO) is the key components in the next generation flexible payload. In this reason, a study on a flexible LO is needed for the development of the next generation satellite payloads. The agile wide-band frequency synthesizer based on fractional-N PLL should be able to generate the wanted frequency within the wide band such as S-band, C-band, and Ku-band. Also, in order to design radiation hardened frequency synthesizer, we use design technique such as radiation hardening by design (RHBD), radiation hardening by process (RHBP), and radiation hardening by shielding (RHBS).
To enhance phase noise characteristic in VCO, the current source is eliminated to reduce 1/f noise from bias line. But this architecture has other problems in VCO performance such as pushing and pulling figure, and process variation. So we use low drop-out (LDO) regulator with 2-bit output voltage control circuit in supply of VCO. Thus, output power and current consumption in VCO should be changed according to LDO. And this output current should also be fixed according to oscillation frequency and temperature variation to get stable phase noise performance. However, this circuit requires additional die area and noise source in LDO is not eliminated completely. PMOS cross coupled topology is used for VCO core circuit and using three VCOs to reduce VCO gain variation according to wide range of oscillation frequency from 4 GHz to 6 GHz. 5-bit switched MIM capacitor array in each VCO is used to cover oscillation frequency of 4 GHz to 4.6 GHz, and 4.6 GHz to 5.2 GHz and 5.2 GHz to 6 GHz, respectively. Due to stable operation of LDO, phase noise variation is within 2.4 dB over 1.6 ~ 2.0 V power supply and -40 ~ 85oC temperature range. VCO core including LDO draws 2.8 ~ 5.6 mA according to oscillation frequency from 1.8 V supply voltage.
Frequency synthesizer consists of three VCOs, PTAT bias, LO generation block such as divider and buffer (or drive) amplifier, loop-filter and fractional-N PLL. The Σ-Δ fractional-N frequency synthesizer includes a 20-bit Σ-Δ modulator of third-order MASH type so that it achieves a fine frequency resolution of about 34 kHz. The charge pump using an analog calibration method with two op-amps eliminates output current mismatch. The external loop filter is used to optimize loop bandwidth each selected frequency bands. To calibrate loop bandwidth, the charge pump current and are programmable according to channel frequency. The prescaler including true single-phase clocked (TSPC) type D-type flip-flop (DFF) in N dividers has up to 1.5 GHz operations. The feedback divider consists of 10-bit pulse counter and 4-bit swallow counter.
The integrated frequency synthesizer including three VCOs, LO generation block, bias, I2C, and fractional-N PLL occupies 5.0mm by 2.5mm. And this IC is fabricated using 0.18 μm RF SOI CMOS process.
Summary
This paper presents designed and measured results of a fractional-N frequency synthesizer in SOI CMOS Technology for next generation flexible communication payload. A tuning range from 4 GHz to 6 GHz is achieved using three integrated voltage-controlled oscillator, which enables all frequencies generation bellows 6 GHz by frequency division. Using current mismatch compensation circuit in charge pump, in-band phase noise of -93 dBc/Hz is achieved at 100 kHz offset in fractional-N mode. Also, In order to design radiation hardened Frequency synthesizer, we use design technique such as radiation hardening by design (RHBD), radiation hardening by process (RHBP), and radiation hardening by shielding (RHBS).
Primary author
Dr
Seong-Mo Moon
(Electronics and Telecommunications Research Institute (ETRI))
Co-author
Dr
Yom In-Bok
(Electronics and Telecommunication Research Institute (ETRI))
Peer reviewing
Paper
Paper files:
