Speaker
Mr
Quentin CROENNE
(Nanoxplore)
Description
In a radiative environment, when a particle with a given LET (Linear energy transfer in MeV.cm²/mg) hits the substrate of a circuit, it creates electron-hole pairs along its braking track; this causes current injections between junctions and consequently upsets node voltages. These transients are called SETs (Single Event Transient). For digital circuits like the FPGA core, a SET corrupts the data as it makes a sequential bit to flip. Due to technology down-sizing and reduction of supply voltage, circuits become even more sensitive to radiation.
This work is implemented in ST CMOS 65nm process. In order to improve the reliability of our FPGA, dedicated to the applications in radiative environments, our full custom library have been simulated using IROC software (TFIT). TFIT calculates the currents injections and simulates their effect by running SPICE simulation.
During the hardening process, two kinds of studies were carried out:
• The Single Event Upsets (SEU) that is a direct upset of a sequential logic (configuration of SRAM and Digital Flip Flop (DFF)). For SRAM, the cell under study with the smallest capacitive load was considered as the worst case.
• The Single Event Transient (SET) in the clock and reset networks can have 2 effects: Jitters that occurs at the clock edge and the glitches that occurs between the clock edges. These effects can make a bit error to propagate in DFF. The design efforts are put on the glitches considering a static clock. Thus we are in a worst case situation in which jitters are replaced by glitches. Moreover, in our designs, Jitter occurs rarely compared to the glitches. This is because minimum period of a clock is 5ns whereas the SET duration is less than 300ps for a LET less than 58 MeV.cm²/mg in normal incidence. Besides, an upset on reset signal can reset a DFF storing “1”. The smallest clock glitch to write in DFF is 150ps. Hence the glitches longer than 150ps are considered as a SET error. No capacitive and resistive load is added in order to simulate the worst case of the cross section.
SEU and SET effects are studied and radiation hardening is performed on all the library cells that are sensitive to these effects:
• SEU in configuration memory: configuration memory of our SRAM based FPGA; they are very critical and require a high level of hardening.
• SET on clock/reset buffer and matrix: they propagate clock and asynchronous or synchronous reset into the circuit with a low skew.
• SEU/SET Digital Flip Flop: user register.
In order to improve the reliability, design optimization are made on structure and layout by calculating upset current with TFIT and running SPICE simulation for different positions (step 50nm) and incidence angles (3 tilt angles x 8 rotation angles). TFIT software give an estimation of the normal and average angular cross sections. The cross section represents the whole sensitive area (normal to the incidence) through which a particle impact causes an SEU/SET. Thus the cross section of the structures is reduced by alternately improving layout and running simulation under 1.08V, lowest supply voltage, typical corner and 25°C. The layout is optimized by putting more distance between sensitive nodes and by bringing the tap closer to them. The results of worst cross section among the different states for the different cell show a great improvement of the radiation hardness.
Primary author
Mr
Quentin CROENNE
(Nanoxplore)
