Speaker
Mr
Eric Savasta
(e2v)
Description
In partnership with CNES, a new ADC has been developped to meet the high dynamic range as well as channel integration requirements of telecommunications payloads.
It is a dual channel single core 12bit 1.5GSPS designed by e2v on ST Microelectronics BiCMOS9 technology which features 0.13µm CMOS and SiGeC NPN HBT bipolar technology (Ft/Fmax = 166/175GHz).
The device is built in a hermetic flip-chip package using Aluminum Nitride material in order to reach optimized thermal performance and higher pin density.
A new European Flip-Chip assembly line is being used for this device.
The paper will develop the following aspects :
- Target noise power ratio performance in multiple Nyquist zone.
- Cross talk isolation in excess of 80dB at 2GHz.
- Chosen ADC architecture.
- Introduction of chained ADC synchronisation for antenna arrays (patent pending).
- System benefits of S-Band high dynamic range digitization.
- Mitigation of radiation effects on ST Micro BiCMOS9 technology.
- Choice of package technology.
- Challenges of Flip-Chip assembly at space level.
Summary
In partnership with CNES, a new dual channel single core 12bit 1.5GSPS ADC is designed by e2v on ST Microelectronics BiCMOS9 technology, and assembled in Flip-Chip hermetic technology.
This device is S-Band capable and features cross talk isolation in excess of 80dB.
The BiCMOS9 technology used features 0.13µm CMOS and SiGeC NPN HBT bipolar technology (Ft/Fmax = 166/175GHz).
The device is assembled in a hermetic flip-chip package using Aluminum Nitride material in order to reach optimized thermal performance and higher pin density.
Primary authors
Mr
Eric Savasta
(e2v)
Mr
Gregory Wagner
(e2v)
Mr
Marc Stackler
(e2v)
Mr
Nicolas Chantier
(e2v)
Dr
Romain Pilard
(e2v)
Co-author
Ms
Florence Malou
(CNES)
