Speaker
Prof.
Ran Ginosar
(Ramon Chips)
Description
RC64 is designed as a high performance rad-hard manycore DSP processor for space applications. Software Defined Radio (SDR) and modems constitute very demanding applications. This paper investigates the implementation of DVB-S2/DVB-S2x modems on RC64. An LDPC hardware accelerator is included in RC64 to support efficient modems, and as a result RC64 achieves in excess of 2 Gbps transmit rate and 1 Gbps receive rate.
The RC64 DVB-S2 modem has been developed using a multi-level methodology and simulators. The paper presents the simulator, the modem algorithms, implementation details, parallel programming of the model, and performance evaluation.
The RC64 DVB-S2 simulator includes a data generator that creates baseband frames. A transmitter encodes and modulates the frames according to DVB-S2 and DVB-S2X standards. A channel simulator adds noise and impairments. A receiver demodulates and decodes the signal, and an analyzer compares the sent and received signals.
The simulator enables testing and performance optimization regarding modem quality (bit error rate for a range of channel impairments, signal to noise ratio and bandwidth), modem bitrate (performance of RC64 executing the modem application), bottleneck analysis (identify required accelerator(s) for the modem) and hardware accelerators type and capacity (validation before hardware integration).
Modem development is carried out through six levels of refinement. Algorithm development starts by coding in Matlab a high level model of the modem, and proceeds through stages until finally parallel C code is employed to program the actual RC64. We start with an unrestricted algorithm, implemented in Matlab (level 1). The accelerators code is replaced by a Matlab executable (mex) file generated from RTL descriptions of the accelerators. Level 1 serves as golden model, to which subsequent level models may be compared.
Level 2 takes into account architectural restrictions of RC64 such as limited memory and real-time constraints. For instance, receiver input samples are processed in pre-defined sample groups rather than in frame size sample groups. In the third level, Matlab floating-point computations are replaced by Matlab fixed point at a word precision of 16 bits, compatible with high-speed arithmetic on the DSP cores of RC64. Accelerator models are replaced by more precise ones driven from RTL. Outputs are carefully compared with the results of the floating-point models, to assure minimal signal degradation.
At level 4, Matlab is replaced by code in the C language, compatible with the compiler for the DSP cores in RC64. The Matlab simulator models of the transmitter and receiver are replaced by models for the cycle accurate simulator of RC64. The output must be exactly the same as produced in level 3. The accelerator code is a function in C representing the hardware accelerator.
At level 5, the code is parallelized to execute on RC64 and further optimizations are performed to take advantage of specific hardware features of the DSP cores. The accelerators function is executed as a separate task, in parallel with other tasks. In level 6 the entire modem is executed on RC64 hardware.
Summary
A DVB-S2 modem on RC64 achieves 2 Gbps transmit rate and 1 Gbps receive rate. The implementation demonstrates how to program a complex multi-stage DSP application for the RC64 manycore.
Primary author
Mr
Peleg Aviely
(Ramon Chips)
Co-authors
Ms
Olga Radovsky
(Ramon Chips)
Prof.
Ran Ginosar
(Ramon Chips)
