12–16 Jun 2016
Gothenburg, Sweden
Europe/Amsterdam timezone

Radiation Hardened by Design Pipeline Analog-to-Digital Converter Blocks in CMOS 0.18µm Technology

14 Jun 2016, 11:30
1h
Gothenburg, Sweden

Gothenburg, Sweden

Poster AMICSA: Implementation of Radiation Hardening on analogue circuits at cell-, circuit-, and system design level Exhibition

Speakers

Prof. Hélène TAP (INP-ENSEEIHT LAAS)Dr Olivier Bernal (INP-ENSEEIHT LAAS)

Description

CCD sensors embedded in satellites need not only to convert analog signals into digital ones with high precision and speed (around 14 bits at 5 MS/s) but also they must be radiation hardened due to the space environment. To achieve such performances, pipeline analog-to-digital converters (ADCs) are usually employed as it is shown in figure 1. ![Overview of the most used architectures depending on the required performances [Murmann2015]][1] The typical block diagram of a 1.5 bit stage for Pipeline ADC is shown in figure 2. ![A 1.5 bit stage for Pipeline ADC][2] From such architecture, the components that have the greatest influence on the ADC performances and the most sensitive blocks to radiations can be identified. Firstly, analog CMOS switches used in such ADCs suffer from both charge injection and drain-source resistance that depend on the input signal level. In addition, a sufficient overdriving voltage of CMOS switches might be difficult to obtain for low power supply voltage. Consequently, bootstrapped techniques are necessary but could not be applied directly for circuits operating in a radiative environment. We have thus proposed a bootstrapped switch architecture that avoids any overshoot voltage at any time (Fig.3) to prevent single event effects. It should ensure a greater radiation hardness of bootstrapped switch architectures. In particular, it was shown that some transistor sizes should be carefully chosen and a simple method to calculate them has been proposed [Bernal2014]. ![Proposed Bootstrapped Switch Schematic (proposed improvements in lighter tone) [Bernal2014]][3] Secondly, in order to improve further the reliability of the main stage amplifier and reduce its power consumption, a predictive amplifier based on a one-stage amplifier architecture was chosen and designed instead of a very high gain two/three stages amplifier. A correlated double sampling (CDS) [Nagaraj1987] has been used here to decrease errors from finite operational amplifier gain. It results in a predictive rail to rail amplifier with switched capacitances. Simulation results show that this technique has reduced by at least 4 times the amplification error of a pipeline stage compared to the non-predictive approach, which implies a 2-bits accuracy improvement. Finally, in radiation environment, comparators can have a high number of errors. We have implemented the radiation hardened approached proposed in [Olson2008] that aims to reduce the bit error rate of a comparator operating in a radiation environment (fig.4). It relies on a dual path design technique to reduce the vulnerability of floating nodes in the switched-capacitor input network of the comparator. Further, an auto-zero approach has been added up to reduce the comparator offset. ![Auto-zero comparator with Dual-path hardening around the preamplifier][4] To validate the performances given by simulation results, a bootstrapped switch and a classical one, an auto-zero comparator with dual-path hardening and a classical one, a predictive rail to rail amplifier with commutative capacitances and a single rail to rail amplifier, have been implemented in a 0.18µm CMOS process (fig.5). ![Die photograph of radiation Hardened pipeline ADC blocks][5] **Acknowledgments:** The authors would like to thank CNES and Thales Alenia Space for their financial support. **References:** [Murmann2015] B. Murmann, "ADC Performance Survey 1997 – 2015" [Bernal2014] Bernal, O.D. ; Perbet, L. ; Tap, H., “Radiation hardened bootstrapped switch in 0.18μm CMOS process, Electronics”, 21st IEEE International Conference onCircuits and Systems (ICECS), 7-10 Dec. 2014, pp 610 – 613. [Nagaraj1987] K. Nagaraj, “Switched-capacitor circuits with reduced sensitivity to amplifier gain,” IEEE Trans. Circuits Syst., vol. CAS-34, pp. 571–574,May 1987. [Olson2008] B. D. Olson et. al., “Single-Event Effect Mitigation in Switched-Capacitor Comparator Designs,” IEEE Trans. Nucl. Sci., vol. 55, No. 6, pp. 3440–3446, Dec. 2008. [1]: https://static.wixstatic.com/media/33c0ce_de3e4fd7d8954047b8eb855794fd1be2.jpg/v1/fill/w_600,h_370,al_c,q_80,usm_0.66_1.00_0.01/33c0ce_de3e4fd7d8954047b8eb855794fd1be2.jpg [2]: https://static.wixstatic.com/media/33c0ce_ca13523667394405a94068ecddc7720e.jpg/v1/fill/w_600,h_293,al_c,q_80,usm_0.66_1.00_0.01/33c0ce_ca13523667394405a94068ecddc7720e.jpg [3]: https://static.wixstatic.com/media/33c0ce_db7090a6251f44d2a6bfdd5f663f6d23.jpg/v1/fill/w_330,h_283,al_c,q_80/33c0ce_db7090a6251f44d2a6bfdd5f663f6d23.jpg [4]: https://static.wixstatic.com/media/33c0ce_500714262be94f4fa5f402e1250d4e98.jpg/v1/fill/w_600,h_225,al_c,q_80,usm_0.66_1.00_0.01/33c0ce_500714262be94f4fa5f402e1250d4e98.jpg [5]: https://static.wixstatic.com/media/33c0ce_2ce7cb9100864fdb886e98dabd620dd5.jpg/v1/fill/w_340,h_255,al_c,q_80,usm_0.66_1.00_0.01/33c0ce_2ce7cb9100864fdb886e98dabd620dd5.jpg

Primary author

Mr Lucas Perbet (INP-ENSEEIHT)

Co-authors

Prof. Hélène TAP (INP-ENSEEIHT LAAS) Dr Olivier Bernal (INP-ENSEEIHT LAAS)

Presentation materials