Speaker
Mr
Bram Faes
(KU Leuven)
Description
Many of today's applications require high precision time-domain signal processing circuits like particle detectors in high-energy physics experiments such as the CMS and ATLAS experiments at the Large Hadron Collider (LHC) in CERN or laser-ranging sensors. The key information of these applications is contained in the timing difference between multiple signals or events. This timing information is usually converted to binary data using time to digital converters (TDC). In large and/or complex systems however, the distance between the detector/event generator and the TDC can become rather large, calling for a highly time accurate, long distance, transfer of these signals.
Many applications now use Low Voltage Differential Signaling (LVDS) and Scalable Low Voltage Signaling (SLVS) for data transmission because of its robustness to interferences, low power consumption and high speed. The SLVS standard is comparable to the LVDS standard, with the difference of a 200 mV common mode voltage and 200 mV voltage swing instead of 1.2 V common mode and 400 mV swing. For data transmission applications, the regenerative nature of the receiver allows some tolerance to jitter provided the bit error rate remains low. However, in the envisaged sub-nanosecond timing applications, jitter is the major impairment to the performance of the system. When an LVDS/SLVS receiver is used in the signal path between the event generator circuit and the TDC, any time distortion introduced by the receiver, will cause a time measurement error and consequently will lower the system resolution. To allow an accurate time measurement, the propagation delay of all the edges, at the output of the LVDS/SLVS receiver, must be the same.
This paper focuses on the design of a radiation hardened by design LVDS/SLVS receiver which can be used in high resolution time measurement applications. This design uses a NMOS input pair, single ended output op amp structure where the output currents can be tuned in order to achieve an equal propagation delay between the rising and falling edges at the output of the receiver. In radiation environments, the total ionizing dose (TID) will change the gain/propagation delay of the receiver, due to shifts in the threshold voltage and degradation of the charge carrier mobility. This will introduce a propagation delay mismatch between the rising and falling output edges. To compensate this mismatch, a replica receiver is added which is capable of measuring the difference in propagation delay between the two edges. When the propagation delays of the rising and falling edges are equal, an ideal clock at the input of this replica receiver must generate a clock signal at the output with a duty cycle of 50 % and a common mode voltage of $V_{DD}/2$. Any mismatch in this duty cycle, caused by the TID effects, will be measured by the integrating feedback loop and will be used to adjust the currents through the receiver in order to equalize the propagation delays of the output rising and falling edges.
The proposed receiver is designed and simulated using a commercial 65 nm CMOS technology. This technology has a power supply of 1.2 V which is identical to the common mode voltage of an LVDS signal. In this design, for an optimal use of the NMOS input pair receiver, the common mode voltage of the input signals must be between $\pm$ 0.5 V - 1 V. This is fine for ad-hoc systems, like the CMS and ALTAS detectors at CERN, which don't need to communicate with off-the-shelve LVDS modules, and so can freely choose the common mode level. Nevertheless, the proposed technique is easily scalable to I/O devices or other technologies with a larger power supply for full LVDS compatibility. Additionally, a PMOS input pair receiver is designed which is able to receive low common mode voltage and SLVS signals. The proposed receiver is capable of supporting event rates equivalent to a 2.56 Gbps data rate with less than 400 fs output RMS jitter and 500 $\mu$W power consumption from a 1.2 V power supply.
Summary
This paper proposes a novel 2.56 Gbps, radiation hardened by design, LVDS/SLVS receiver. Simulation results show a 500 $\mu$W power consumption and a 400 fs RMS output jitter. The propagation delay difference, due to radiation effects, of the rising and falling edges at the output is compensated using a replica receiver with compensation loop. The final paper will include an extended explanation on the behavior of the replica receiver and its feedback loop including simulation results.
Primary author
Mr
Bram Faes
(KU Leuven)
Co-authors
Mr
Jorgen Christiansen
(CERN)
Prof.
Patrick Reynaert
(KU Leuven)
Prof.
Paul Leroux
(KU Leuven)
Mr
Paulo Moreira
(CERN)
Peer reviewing
Paper
Paper files:
