SEFUW: SpacE FPGA Users Workshop, 3rd Edition

Session

Design Experiences

15 Mar 2016, 10:50

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Conveners

Design Experiences

• David Merodio Codinachs (ESA)

Design Experiences

• Agustin Fernandez-Leon

35. Implementation of Space-Industry IP : A Comparison of Space-Grade FPGAs

Dr Rajan Bedi (Spacechips Ltd.)

15/03/2016, 10:50

The number and diversity of space-grade FPGAs offer many options when architecting satellite sub-systems. One-time programmable anti-fuse, flash and SRAM-based technologies, each with unique fabrics, present many interesting trade-offs when selecting the most appropriate device for your next mission. Today, space-grade FPGAs are formally available from 350 µm to 28 nm nodes with advertised...

57. FPGA development flow for future large space FPGA

Mr Florent MAnni (DC/TV/IN)

15/03/2016, 11:20

The FPGA available for Rad-tolerant or Rad-Hard applications are quite small (with regard to their commercial brothers). Some are SRAM based, many are antifusible based. The development flow described inside the ECSS-Q-60-02 standard is well fitted for this kind of targets. The next generation of FPGA for space application will include bigger FPGA matrix most of them SRAM or flash based. The...

41. Prototyping a SOC on RTAX4000D for Solar Orbiter's Low Frequency Receiver.

Mr Alexis Jeandet (Plasma Physics Laboratory)

15/03/2016, 11:45

Many space instruments using FPGA rely on the RTAX family, from the RTAX-250 to the RTAX-2000D but none of them embed a **RTAX-4000D**. For the first a RTAX-4000D will be onboard the [Solar Orbiter](http://sci.esa.int/solar-orbiter/) spacecraft in the Low Frequency Receiver instrument(**LFR**) developed at the Laboratory of Plasma Physics([LPP](http://www.lpp.fr/)). The LFR is in charge of...

74. LEON3/GRLIB for Space-Grade Programmable Devices Update and Roadmap

Mr Jan Andersson (Cobham Gaisler AB)

15/03/2016, 12:10

Cobham Gaisler develops the LEON3FT SPARC V8 fault-tolerant microprocessor that is available both as IP cores part of an IP library (GRLIB) that allows users to design their own custom system-on-chip (SoC) designs, and also as part of ready-made designs and devices. The GRLIB library currently provides template designs that allow users to target Xilinx Virtex-5QV, Microsemi RTAX, RT ProASIC3...

44. Resource-Efficient Debugging Core to Evaluate FPGA Designs in On-Board Processors

Mr Florian Rittner (Friedrich-Alexander-Universität Erlangen-Nürnberg)

16/03/2016, 12:35

Modern SRAM-based FPGAs improve on-board processing (OBP) in space applications through dynamic reconfiguration of the firmware. This provides flexibility and adaptability for new communication experiments. An example for such a novel signal processing platform is the *Fraunhofer On-Board Processor* (FOBP), located in the scientific payload part of the *Heinrich Hertz* satellite mission, with...