Speakers
Dr
Antonio Sánchez
(IUMA/ULPGC)Mr
Yúbal Barrios
(IUMA/ULPGC)
Description
Reprogrammable Field Programmable Gate Arrays (FPGAs) for space applications, are becoming steadily more common in space applications due to their high flexibility to change dynamically the functionality of the on-board system, combined with high performance and low power consumption. SRAM-based FPGAs) are vulnerable to radiation, which can cause bit flips in the configuration memory, resulting in a malfunction of the system or a functional interrupt. Nevertheless, currently several techniques may be implemented to prevent or mitigate the impact of a SEE, such as scrubbing to inspect the configuration memory or Triple-Module Redundancy (TMR) schemes in the logic fabric to preserve the data integrity.
Moreover, the FPGA design methodology has been evolving in the last years, addressing the complexity of the hardware architecture in a higher level of abstraction than RTL traditional models. This design methodology, named High-Level Synthesis (HLS), allows generating a compliant hardware description from a reference software code (for example written in C/C++), with few modifications oriented to a hardware-friendly implementation. This constitutes a new design flow, which may potentially reduce the Time-To-Market (TTM) with respect to the traditional RTL design, taking advantage of both reconfigurability and early prototyping. However, the effectiveness of the hardware implementations by means of HLS tools has still to be assessed.
This work presents a comparative study of different hardware implementation approaches using different design flows and target FPGA technologies. As target applications to conduct the study, two lossless data compression standards developed by the CCSDS (Consultative Committee for Space Data Systems) have been chosen. These standards are intended for space applications, and therefore they have been designed with the aim of providing a good trade-off between compression efficiency and computational complexity. Among them, the CCSDS-121 standard compresses of raw uni-dimensional data, while the CCSDS-123 has been specifically designed for multispectral and hyperspectral images. In addition to the two lossless standard, a proposed extension of the CCSDS-123 standard for lossy compression has been also used as additional case study.
A comparative study is conducted among hardware implementations of the CCSDS-121 and CCSDS-123 compression standards on several FPGA technologies (Microsemi RTAX and RTG4, Xilinx Virtex and ZynQ families), following both RTL and HLS design methodologies (CatapultC and Vivado HLS). The work is complemented with the implementation results of the CCSDS-121 standard over the space-grade BRAVE NG-MEDIUM FPGA, the first medium-capacity, high-performance and radiation-hardened re-programmable European FPGA. The results of this work have been obtained in different national and European projects in which the research group is present, such as TRP-AO8032, part of the ESA program, the European funded project ENABLE-S3, or the Spanish funded project REBECCA.
Primary authors
Dr
Antonio Sánchez
(IUMA/ULPGC)
Mr
Yúbal Barrios
(IUMA/ULPGC)
