Single Event Transients (SETs), originating in combinational logic as a result of the passage of energetic particles, represent nowadays a serious reliability issue for electronics operating under radiation exposure. In that regard, analysis of the SET generation and propagation effects in combinational logic is an important step in the rad-hard design. To enable efficient SET evaluation, the SET generation and propagation models based on analytical formulations or look-up tables are used. In this work, the modeling of the SET generation effects in standard combinational logic gates designed in 130 nm CMOS process from IHP is addressed. The models for the two main parameters of SET generation (critical charge and SET pulse width) are introduced. The proposed models are derived through the conventional current-injection approach in SPICE simulations, and they provide advancement over the state-of-the-art models by considering important aspects that have been neglected in existing models.
The critical charge models are used to predict the minimum induced charge required to cause the SET voltage glitch at the output of a logic gate. A number of critical charge models have been proposed in literature. However, existing models have some important shortcomings such as: (a) some models do not consider all relevant parameters (e.g. load and temperature), (b) some models depend on technology-related parameters which are often not readily available to designers. As alternative to existing models, we introduce a model based on the linear superposition principle, i.e. the critical charge QCRIT is expressed as a sum of contributing components. The proposed model was derived from SPICE simulations with the double-exponential current source, and considers the dependence of QCRIT on 6 parameters: size factor of target gate ST, size factor of load gate SL, interconnection capacitance CW, supply voltage VDD, temperature TEMP and width of the injected current pulse TPULSE.
As the critical charge gives only the information on the circuit node’s robustness to direct particle strikes, the knowledge of the SET voltage pulse width is required to estimate the probability that a generated SET voltage pulse will eventually cause a soft error. Most available SET pulse width models have been derived using the double-exponential current source as a SET current model. Although the double-exponential current model is useful for initial estimation of QCRIT, its inherent limitations lead to inaccurate prediction of the SET pulse width. Recently, a SET pulse width model considering the bias-dependence of the induced current pulse has been proposed by T. R. Assis et al. (IEEE IRPS, 2016), but this model requires extensive calibration with TCAD simulations. In contrast to existing models, we propose a simple SET pulse width model derived from the current injection in SPICE using the bias-dependent current source proposed by J. S. Kauppila et al. (IEEE TNS, 2009). The proposed model expresses the SET pulse width in terms of particle’s LET, drive strength of target gate ST and supply voltage VDD.
Extensive evaluation of the proposed models’ accuracy with respect to SPICE results has been conducted. The proposed critical charge model provides very good accuracy (better than 90 %) for lower driving strengths of the target gate but the accuracy is lower for higher driving strengths. To resolve this issue, we intend to implement an error function for compensating the relative error. On the other side, the proposed SET pulse width model provides very good accuracy (better than 90 %) for higher values of LET but the relative error is higher for low LETs (LET < 2 MeV cm2 mg-1). This issue is currently under investigation. Overall, the proposed models can be very useful for initial estimation of the SET generation effects in standard combinational gates. With improved accuracy, the models can be integrated into a design flow for automated estimation of the soft error rate (SER) of complex logic circuits.