17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

FPGA Based Reconfigurable On-Board Payload Processing for an Exploratory In-Orbit Verification of an E-Band (71-76 GHz) Satellite Link (EIVE)

18 Mar 2020, 10:30
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Reconfiguration Reconfiguration

Speaker

Ms Laura Manoliu (University of Stuttgart)

Description

To develop new frequency bands for broadband satellite communications and to ensure the constantly growing demand for higher data rates, the EIVE project proposes the world’s first in-orbit verification of a communication link in E-Band on a CubeSat system. A data downlink is planned in the frequency range of 71-76 GHz, allowing 5 GHz radio frequency data bandwidth, from a nanosatellite to a ground station. The main purpose of the mission is to evaluate the influence of the atmospheric effects on different modulations formats but also the transmission of uncompressed, high resolution 4K video data via the E-Band link, for future Earth observation services or inter-satellite links. A reconfigurable on-board payload computer based on Field-Programmable Gate Array (FPGA) technology provides the needed flexibility and enables adaptable modulation formats with respective data rates and switching / routing of the digital processing chain. The digital signal processing for the E-Band link is entirely performed by the payload FPGA, independent on the on-board computer and it only communicates with the on-board computer by means of a Universal Asynchronous Receiver-Transmitter (UART) protocol. An Arbitrary Waveform Generator (AWG) is implemented on the payload FPGA and the waveform patterns are integrated in a memory block and played-back cyclically via a high-speed interface. The baseband signal has up to 3 GHz bandwidth and the digital-to-analog converter (DAC) has a resolution of 8 bit and a sampling rate of 12 GSa/s.
A trade-off analysis between two FPGAs is also shown and the suitable type is chosen according to the application requirements. A DAC is chosen in harmony with the selected FPGA. The presentation introduces the system design, the requirement engineering, the design flow, the different interfaces integration and the planned qualification tests for the payload computer of the extremely high data rate satellite link. The EIVE satellite is scheduled to fly in 2021.

Primary authors

Ms Laura Manoliu (University of Stuttgart) Mr Benjamin Schoch (University of Stuttgart) Mr Ulrich Mohr (University of Stuttgart) Mr Sébastien Chartier (University of Stuttgart) Prof. Ingmar Kallfass (University of Stuttgart) Mr Ralf Henneberger (RPG, Radiometer Physics GmbH)

Presentation Materials

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