Developing FPGAs which work across reliably in flight requires considerable thought. Reinforcing this challenge is that 84% of commercial FPGA designs make it to production with a non trivial error (source mentor graphics / wilson group survey).
To reduce the risk of a fault making it to flight or being found very late in the program. There need to be a number of rules followed for best coding practices, coding practices for safe synthesis, and design review check lists. This is before we get to safely analyzing the Clock Domain Crossing which is prevalent in modern FPGA Designs.
Failure to follow these simple rules can lead to failures in orbit like the NASA WideField Infrared Explorer which failed due a logic design error and reliance on the default values during power up.
Static Analysis can help address these issues and also save considerable time later in the implementation flow and improve the quality of code which enters simulation and synthesis. With static analysis we do not need to ask the right question like we do in simulation just agree the applicable coding rules.
This presentation will demonstrate how a static analysis tool has been used to create a rule set which has then been applied to the eight high priority IP in the ESA IP Catalog. The presentation will present preliminary results on the decisions behind the implemented rule set and tool flow along with results from the first tranche of IP verification along with suggested improvement which could be made.