17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

Development and FPGA Roadmap for LEON5FT and NOEL-V Processor Models

17 Mar 2020, 10:50
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Industrial Experiences Industrial Experiences


Mr Martin Ronnback (Cobham Gaisler)


Cobham Gaisler has developed two new processor models. LEON5 is a continuation of the LEON line of SPARC processors and NOEL-V is the first implementation from Cobham Gaisler of the open RISC-V instruction set architecture.

As with earlier generations of processor IP core implementations from Cobham Gaisler, the new processor models target both FPGA and ASIC target technologies. Since the implementations are more complex compared to earlier generations of processors, focus has been on high-capacity FPGAs such as the Xilinx Kintex Ultrascale.

The presentation will show characteristics and performance results for NOEL-V and LEON5 and discuss the current FPGA implementation results, radiation mitigation strategies and a roadmap for the mitigation strategies that are planned to be evaluated and implemented.

Primary authors

Mr Martin Ronnback (Cobham Gaisler) Mr Nils-Johan Wessman (Cobham Gaisler) Mr Magnus Hjorth (Cobham Gaisler)


Mr Jan Andersson (Cobham Gaisler)

Presentation Materials

There are no materials yet.