17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

UVVM usage is exploding. A brief introduction and all the new stuff for this standardised VHDL verification methodology.

18 Mar 2020, 12:10
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Design Flow Design Flow


Mr Espen Tallaksen (Bitvis)


Verification is critical for an acceptable FPGA quality. Unfortunately, achieving a good FPGA quality is often very time consuming. However, with a good testbench architecture the workload could be reduced significantly. UVVM provides the best VHDL testbench architecture possible and also allows a unique reuse structure. Entry level UVVM is dead simple even for beginners, and for more advanced verification, the standardised Verification Components, the high level SW-like commands and all the other features will allow even really complex verification scenarious to be handled in a structured and understandable way. UVVM is open source and provides a testbench kick start with open source BFMs and verification components for UART, SPI, AXI-lite, AXI stream, Avalon MM, Avalon stream, I2c, GPIO, SBI, GMII and Ethernet.

UVVM has been significantly updated through ESA’s UVVM extension project. We have previously released the Scoreboard, and now lots of other new functionality has also been added. The most important of these are activity watchdog, Error injection, Monitor, Hierarchical VVCs and Specification Coverage.
This presentation will give you a fast introduction to UVVM Utility library, BFMs and VVCs, and then go through the new features and explain how they will help you making a better testbench - and develop this much faster.

Primary author

Mr Espen Tallaksen (Bitvis)

Presentation Materials

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