17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

A UML Profile for VHDL FPGA Designs.

17 Mar 2020, 12:35
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Design Flow Design Flow

Speaker

Mr Harald Ottacher (Space Research Institute / Austrian Academy of Sciences)

Description

To perform the design of an FPGA project, several graphical representations of the later coded implementation of the FPGA function can be used.
The usage of hardware description languages for the implementation enables also design approaches and representations that are used for software designs, as a basis for the FPGA implementation, like the well defined Unified Modeling Language (UML).
To improve the design process at our institute and support the code generation by tools a UML 2.0 profile for VHDL was adapted to define a detailed design model of the VHDL implementation.
The profile defines the structural view of the implementation with UML class diagrams and the behavior of the units with state diagrams.
These diagrams represent the structural and behavioral implementation of the VHDL code in the design phase. A set of defined transitions of the model elements into the VHDL code allows an automatic generation of the VHDL files from the model.
The presentation will give a short overview of the used UML profile and the transition rules. A short presentation of realized projects in the frame of developed scientific instruments and lessons learned on this design guideline concludes them.

Primary author

Mr Harald Ottacher (Space Research Institute / Austrian Academy of Sciences)

Co-author

Jorge Tonfat (Space Research Institute / Austrian Academy of Sciences)

Presentation Materials

There are no materials yet.