17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

The data processing unit for the PMI instrument aboard the Lagrange mission

18 Mar 2020, 17:10
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
FPGAs: High Performance FPGAs: High Performance

Speaker

Juan Pedro Cobos Carrascosa (Institute of Astrophysics of Andalusia)

Description

The Photospheric Magnetic Field Imager (PMI) will be one of the payload instruments onboard the Lagrange mission. It will provide magnetograms and tachograms of the solar photospheric plasma as valuable information for being used in space weather diagnostics. The Polarimetric and Helioseismic Imager onboard Solar Orbiter (SO/PHI) is the major heritage instrument for PMI. Its DPU, however, does not provide the necessary processing power to cope with the operational real time requirements of PMI. Thus for PMI the development of an updated DPU is necessary, based on more powerful FPGAs and enhanced efficiency of the architecture.
The SO/PHI DPU hardware architecture uses a Leon-3 FT (GR-712) core for control tasks, in combination with an RH OTP FPGA that acts as system supervisor. The advanced data processing is done within two radiation-tolerant, in-flight reconfigurable, Xilinx Virtex-4 (XQR4VSX55) FPGAs and they reach high-performance computing resolving extremely complex algorithms. The aim is to optimize the existing design approach of SO/PHI for PMI by reusing as much as possible. But the most important drawback is that Virtex-4 manufacturing is discontinued and we cannot use it any more.
The current DPU proposal (indeed one among the two options in a pre-development study) is more conservative and uses only one Virtex-5 as a baseline. This device is already being used in several missions and its availability is immediate. Compared to SO/PHI, it reduces the number of DPU building blocks to two: the system controller and one reconfigurable FPGA at the expense of optimizing the number of reconfigurations. This proposal tries to improve the time-space partitioning scheme used for SO/PHI based on the lessons learned about the data processing onboard.
On the other hand, the Kintex Ultrascale FPGA is the other candidate to consider. In this case, the FPGA resources are far more numerous and powerful but it is not a radiation-hardened device by design. Hence, a thorough study about design balance between protection to errors induced by radiation and computing performance is needed.
We are also considering to move from a GR712 to the new GR740 where we would use 4 Leon cores. This obviously represents a good advantage since we can move some tasks from firmware to software if needed and provided the feasibility from a time requirement point of view.
Regarding the bus connection between FPGA and processor, we consider to keep the Memory Mapped I/O but we are also evaluating the possibility of using PCI which looks more suitable. One of the major challenges of our design is that neither GR712 nor GR740 has specific capabilities for programming the FPGA directly. We are contemplating the use of a multi-booting scheme based on SPI memories and we are even experimenting with bit-banging the JTAG from the Leon’s GPIO.
In summary, we present how the next generation of Xilinx devices can provide great computing capabilities which can simplify the PMI DPU design without compromising its performance. We point out some design challenges (buses, re-programmability, and scheduling of the time-space programing) and the necessity of studying the trade-off between computing performance and error protection.

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