SEFUW: SpacE FPGA Users Workshop, 5th Edition

FPGA continuous integration

18 Mar 2020, 11:50

20m

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Design Flow Design Flow

Speaker

Florent MAnni (DC/TV/IN)

Description

In the beginning of this year, CNES conducted a one month project with three Students from Enseeiht School. The purpose was to try and gather feedback about continuous integration of FPGA development. The use case was a RiscV ioptimized processor targetting NanoXplore Medium FPGA. The tools used for this presentation were: Git, Gitlab,Gitlab-Ci,Doxygen,Sonarqube-Rulechecker,Cocotb,Nxmap,Ghdl. The presentation provides description and feedbacks about this use case.