17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

FPGA continuous integration

18 Mar 2020, 11:50
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Design Flow Design Flow


Florent MAnni (DC/TV/IN)


In the beginning of this year, CNES conducted a one month project with three Students from Enseeiht School. The purpose was to try and gather feedback about continuous integration of FPGA development. The use case was a RiscV ioptimized processor targetting NanoXplore Medium FPGA. The tools used for this presentation were: Git, Gitlab,Gitlab-Ci,Doxygen,Sonarqube-Rulechecker,Cocotb,Nxmap,Ghdl. The presentation provides description and feedbacks about this use case.

Primary author

Florent MAnni (DC/TV/IN)

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