Speaker
Description
This ADC is composed of mainly 2 blocks:
• An 8:2 analog mux combined with an auto zeroed-amplifier (0dB, 6dB and 12dB).
• A 500kS/s ADC with an internal voltage reference generator (external capacitor free) configurable in differential or single-ended mode 11-bit SAR ADC or in 14-bit SAR ADC (in such configuration the sampling rate is limited to 300kS/s).
All the digital is hardened against SET, SEU and SEL:
• Only radiation-hardened flip-flops (HIT) are used.
• Data out bits are SET-free by means of a Muller-C filter.
• Clock paths hardened by drive strength.
• Signals driving the switches connecting the capacitors to the voltage reference are not SET free up to 60 MeV*cm2/mg. However, any SET on these signals will be filtered thanks to the limited analog bandwidth of the capacitor bank.
The 14-bit pseudo-SAR ADC is essentially an 11-bit classical SAR ADC (already existing component from the DARE180U library) combined with a 3 bits sub-DAC. The main SAR ADC (11 bit) uses a unit cap of 12.5fF and has 2 capacitor banks of about 25pF (2048 unit cap). The intrinsic matching of these capa banks is well above the 11 bit of the original ADC and allows us to reach an accuracy of 14 bit. To add these 3 extra bits on the existing 11 bit SAR ADC there are several possibilities:
- Increase the number of unit caps from 2048 till 16384, but it will create a very big sampling capacitor (2 times 200pF) and furthermore we lose the benefit to reuse a silicon-proven ADC (major change of the layout and the schematic).
- Implement a second capa bank of 8 unit cap connected to the main capa bank of 2048 unit cap thanks to a bridge cap. But in that case the ratio between the 2 capa bank (8/2048) is not optimal and will lead to a loss of accuracy.
- Add a sub-DAC with binary-weighted downscaling of the unit cap. It is difficult to create a smaller capacitor than the unit capacitor and keep a good matching. But as the SAR ADC is based on charge sharing, another solution is to use the unit cap of 12.5fF and to store on it smaller voltage (Q=V*C). This can be easily performed by creating sub-voltage references: the original voltage reference VREFP/VREFN is extended by adding 7 extra intermediate voltages.
On top of that, some extra capacitors (heaving each the same value as the unit cap) have been added in the sub-DAC to have the possibility to add a pseudo-random offset to the sampled signal and to perform at the end a Diethering. The Diethering is intended to reduce the mid-code INL discontinuity.
The comparator has been also slightly redesigned to reduce his equivalent input noise to a 14-bit level.
The capacitor matrix and their switches are insensitive to SEU (i.e. permanent capacitor charge error) except the3 switches on the capacitor bank side connected to the comparator. Indeed, if during the conversion a charge is injected when the switches connecting the capacitors to the voltage references are on, this charge is stored on the capacitor bank. But these switches represent a very small cross-section and will lead to many data corruption
