Speaker
Description
Abstract
A highly integrated, mixed signal IC implements most functions needed for acquisition and for control synchronization in redundant electromechanical actuator applications currently targeting aviation/launch/low Earth orbit. The IC is implemented using circuit and system design techniques to be immune to single events affecting internal circuits and/or communications interfaces. Actuator system design is highly simplified, and system reliability is increased by dramatically reducing the number of components v.s. traditional approach.
Introduction
Electronics for electromechanical actuators usually extend from the sensors for position/velocity to be controlled (usually L/RVDT or resolver) to driving the currents in the windings of an electrical motor and brake solenoid. Typically, besides position, other sensor data related to safe operation of the actuator is needed (e.g. temperature at several points, torque/pressure, currents, voltages etc.). This data is fed to a control algorithm that is executed via software on an MCU or via DSP and state machines if running in an FPGA fabric. Control outputs in the form of PWMs are fed via gate drivers and power devices to the motor/brake. In this type of control, usually, a synchronous sampling scheme is needed to reduce system interactions.
While high-safety, high-reliability electro-mechanical actuator design normally involves a redundant scheme it also requires quite a large amount of IC and discrete devices to cover all functions (see Figure 1). Therefore, there is a need to integrate as many of these functions as possible to reduce size/mass and increase reliability at system level.
A Fully Integrated Analog Front-End IC for Electromechanical Actuators 1
A fully integrated analog front-end shall cover all acquisition functions and support synchronous sampling while implementing a SEU immune interface to the MCU/FPGA processing. Additionally, the IC shall have a simple power scheme while still interfacing with some of the sensors’ larger voltage. Early in the design process the decision was made to not integrate gate drivers and power devices to drive the motor windings to allow the usage of same AFE with different actuator power/voltage level combinations. Also, the level shifting/isolation needed for current and DC line voltage sense is not included in the IC as it is application dependent.
The following is a summary of the functions that are integrated in this circuit (see Figure 2 - AFE block diagram):
• Redundant LVDT/resolver driver with primary voltage sense
• Redundant LVDT/resolver 2 x secondary sense supporting 5/6 wire sensor connections
• Multiple PT100/PT1K channels supporting 2/3/4 wire sensor connections
• Multiple 4-20mA loop sensor interfaces (high side power switch with protection and low side current sense) for other sensors
• Redundant motor DC line voltage sense channels
• Multiple motor winding current sense channels
• Internal DC regulators to support single 10-30V input supply
• Internal register file for ADC conversion results and subsystem status using triple redundant storage
• Fully programmable set of PWM generators that are synchronous with the overall channel acquisition.
• Redundant SEU immune SPI/UART communication interface to host with hardware single error correction / double error detection.
• Internal fault checkers and redundant fault signaling.
This IC implements an extended set of fault-checking for inputs impedances, internal supplies compliance and measurement data range thus detecting open /shorts or parametric faults internally or by using host-level software drivers. Additionally, the AFE sports two dissimilar reference voltage blocks with a cross-checker to detect parametric drift. This way reference value drifts and ADC parametric errors can be detected during normal operation while acquiring data.
For SEU immunity, the higher accuracy channels (LVDT and current sense) are implemented with delta sigma modulators followed by SEU immune decimation filters while the other channels can be fed to one of the two redundant 10-bit SAR ADCs that use triple redundant comparators for the successive approximation decision.
Digital communication (SPI or UART) to the host integrates a single error correction, double error detection hardware encoding to avoid executing incorrect writes from the host and allow for single bit correction of acquisition data received by the host. This is more efficient than the host to operate majority/redundant read/write cycles.
LVDT sensing
The position sensing is done using two independent channels usable as fully independent or as redundant driver / sense. The LVDT drivers can be independently programmed for frequency and waveform and are implemented using a PWM based direct digital synthesis topology with external LC filters. Usually the user will program a sinusoidal waveform and will run a slow amplitude regulation software loop that will update periodically the DDS tables used to synthesize the output waveforms. Overall the circuit can drive up-to 10V RMS sinewave. Two differential voltage acquisition channels are used to sense the DDS generated waveform on the LVDT primaries.
The LVDT secondary channels (2+2) are fed via voltage dividers and some external filtering to per-channel sigma delta modulators. Internally each secondary channel samples a fixed number of samples per LVDT driver period and calculates the true RMS value as the square root of the sum of squares of acquired samples. This is done by a TMR based logic DSP block that implements a first decimation filter, a squarer, an averaging filter with a second decimation and a square root calculation. The RMS value for each of the two secondary channels (A and B) is available as a register value to be read by the host. The actual position calculation is finalized by the host to calculate the relative position as (A-B)/(A+B). Additionally, the host should implement the system level mechanical calibration for position.
The overall position measurement error at system level for one LVDT channel is 1.2E-4xMR and the RMS noise of each sample is below 6.1e-5xMR (where MR is the input measurement range).
The error checkers for LVDT drivers and for sense are able to detect open/short on primary or secondary channels and common mode driver faults for the secondary windings.
Applications
Typical application of LX4580 is a Permanent Magnet Synchronous Motor (PMSM) linear actuator with redundant drive and sense electronics. The full paper will show details of PMSM field-oriented control implemented in software closing the loop with LX4580 and a software-based version of LX4580 synchronization for multi-phase power driver alignment.
Conclusions and Future Work
A highly integrated mixed signal IC with SEU tolerance by design was presented together with results in applications involving electromechanical actuators for aviation/launch and low Earth orbit. Among other blocks it integrates 9 delta-sigma ADCs and 2 SAR ADCs and a single input supply power management scheme allowing to power both internal electronics and all sensors. Position accuracy in system is better than 13 bits and RMS noise is below 1 LSB of 14 bits. Radiation and reliability tests still need to be carried out, preliminary LASER tests predict good SEL immunity, ratiometric measurements and self-calibration for all critical channels should provide good support for total dose performance.
Bibliography
1 “24 Channel Data Acquisition System with Synchronized Motor Control Interface”, LX4580 preliminary datasheet, Microchip Technology Inc., 2021: https://www.microsemi.com/document-portal/doc_download/1244912-lx4580-datasheet
