Speaker
Description
The flash-based mass memory system are very commonly used in PDHU and OBC. We will present a flexible FPGA architecture, which implements the most timing-critical data acquisition, buffering, storage and downlink functions. The architecture has been implemented in a compact and high-performance PDHU, which was presented on DASIA 2019: "A Compact High-Performance Payload Data Handling Unit for Earth Observation and Science Satellites". It has also been implemented in many industry projects, e.g., JUICE mission (on-board computer mass memory board), Biomass PDHU, FLEX PDHU, KACST Satellite Computer Board with mass memory, Mass Memory Module for KARI Kompsat-7, S4Pro (H2020 demo project), Mass Memory Formatting Unit in Copernicus Land Surface Temperature Monitoring (LSTM) and Copernicus Polar Ice and Snow Topography Altimeter (CRISTAL), Copernicus Imaging Microwave Radiometry (CIMR) PDHU as well as Artemis Gateway Mass Memory Storage (MMS). FPGA serves as the central controller and provides the following main features:
- Scalable Flash controller, up to 4 partitions can be supported. The mass memory capacity is scalable.
- Flexible logical to physical address mapping. The parallel accessed flash devices may have different flash block addresses so that flexible wear levelling algorithm can be supported in software.
- Flexible flash access interleaving scheme to maximize the flash interface performance.
- Double symbol error correction (Reed-Solomon) for flash mass memory.
- Flexible packet management: e.g., packet store based file management; logical address based mapping; application identifier based mapping; customized mapping.
- High data rate SDRAM controller for data buffering: SDRAM, DDR2, DDR3 etc.
- All memories (external and internal) are EDAC protected (Hamming / Reed-Solomon).
- Diverse payload interfaces, e.g. WizardLink, SpaceWire, Channel links, Ethernet, SpaceFibre etc.
- Diverse downlink interfaces, e.g. WizardLink, LVDS parallel interface, Ethernet, SpaceFibre etc.
- External SRAM as context memory to amend internal BRAM limitation (especially for Microchip RTAX FPGA).
- Diverse TM/TC interfaces, e.g., MIL-Bus, SpaceWire, Ethernet, UART, HPC (high power command), RSA (relay status acquisition), etc.
- Implementation on RTAX / ProASIC3E / RTG4 FPGAs/Xilinx Kintex FPGA.On RTAX FPGAs, 2.2Gbps data acquisition + 640Mbps data downlink reached in an industry project. On RTG4 FPGAs, aggregate 6Gbps for simultaneous acquisition and downlink. On Xilinx Kintex FPGA, aggregate 20Gbps for simultaneous acquisition and downlink.
- Optional online/offline data compression/encryption.
- Optional SpW Router
Detailed configurations (e.g., interfaces, capacities, data rates, etc) will be presented in workshop. The FPGA architecture has demonstrated its flexibility and scalability not only in previous industrial projects, but also in recent on-going proposals, studies as well as pre-development activities at DSI. We will present the future trends of our FPGA- and flash- based mass memory products.
