Speaker
Description
SpaceWire (SpW) is one of the most widely used communication standard in space applications for on-board data handling. Ensuring that a SpW device is bug-free and highly reliable is crucial to reduce to zero the risk of compromising the space mission.
In this paper, a SystemVerilog Verification Intellectual Property (VIP) supporting the full testing of any implementation of a SpW Codec is presented. The VIP is fully compliant with Universal Verification Methodology (UVM), which represents the current state-of-the-art for functional verification.
The presented SpW CODEC VIP is based on the concept of Twin Model, i.e., a software emulator of an ideal SpW Codec able to communicate directly with the Device Under Test (DUT), which can be any SpW IP core with the Data-Strobe Interface. This approach leads to a significant simplification of the testing because it automatically exchanges with the DUT all the low-level information for establishing and maintaining the communication link, not requiring user effort to continuously adapt input stimuli to the simulation scenario.
In parallel to the main communication link between the DUT and the Twin Model, this VIP includes a Twin Link connecting two Twin Models. The Twin Link emulates the ideal link behavior and is used in simulation scenarios involving communication errors and disconnections. In this way, the Verification Environment automatically compares the functioning of the two links, reporting any malfunctions of the main one that depends on the DUT operations. Without the Twin Link, the user should manually check the correct DUT behavior in case of disconnections.
The result is a highly reliable and configurable VIP that allows for automated testing of all functionalities of any SpW CODEC implementation. In addition, thanks to the full UVM compliance, it has significant advantages in terms of reusability and maintainability.
The features of this VIP have been confirmed by implementing a complete test campaign including more than 150 testcases on two different and unrelated IP Cores: IngeniArs S.r.l. IP core and the one belonging to European Space Agency IP core portfolio. All functional requirements have been covered by at least one test (100% of functional coverage) and both systems resulted compliant with the first release of the standard. In addition, IngeniArs S.r.l IP Core was proven compliant also with the revision 1.
The high user-friendliness of the presented VIP allows the user to define and run new testcases in a very easy way and without knowing the Verification Environment internal architecture. Therefore, it is easy for VIP users to implement their test plans and achieving goals such as full functional and code coverage.
The final result is a significant reduction in verification time and effort of SpW Codec IP Cores and SpW-based systems.
Keywords— Universal Verification Methodology (UVM), SpaceWire (SpW) Codec, Verification IP, Twin Model, Twin Link, Verification Environment, functional verification, reusability, SystemVerilog.
