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Mar 14 – 16, 2023
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Presentations available

SpaceFibre and image compression on RTG4 FPGA (Syderal Polska)

Mar 15, 2023, 5:15 PM
25m
Erasmus High Bay (European Space Research and Technology Centre (ESTEC))

Erasmus High Bay

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
FPGAs: High Performance FPGAs: High Performance

Speaker

Dawid Linowski (Syderal Polska Sp. z o.o.)

Description

As on-board payload complexity and generated data volume increases, the demand for high-throughput data transfer becomes crucial. Higher transfer speeds are required between payload modules (to process data) but also between payload and platform (to store data before sending back to Earth). One of the standard interfaces to achieve this task is SpaceFibre - a multi-Gbps, on-board network technology dedicated for spaceflight applications, which uses electric or fibre-optic cables to provide data-rates up to 6.25 Gbps (and potentially beyond). In addition, this technology is the successor of SpaceWire, not only improving the data rate but also reducing the cable mass and improving QoS and FDIR capabilities while remaining compatible with SpaceWire at packet level.
This work presents results of the SFIC project under the Polish Industry Incentive Scheme (PLIIS). The main goal in the project was to present the SpFi as a high-throughput data transfer protocol used to transmit hyperspectral images to the compression cores realising two lossless data compression standards developed by the CCSDS: CCSDS-121 and CCSDS-123. The CCSDS-121 standard compresses raw uni-dimensional data, while the CCSDS-123 has been specifically designed for multispectral and hyperspectral images. The demonstrator offers capabilities to use either the standalone CCSDS-123 or the combination of both CCSDS-123 as a pre-processor and CCSDS-121 (which creates SHyLoC) and compress hyperspectral images corresponding to two different datasets. Data is fed via SpaceFibre operating at 2.5 Gbps. Achievement of above objectives was demonstrated by VHDL development, integration and hardware tests on an RTG4 FPGA Development.

Primary authors

Dawid Linowski (Syderal Polska Sp. z o.o.) Mr Andrzej A. Wojciechowski Mr Tomasz Rybak

Presentation materials