Speaker
Description
FPGAs are getting more complex with each product generation.
Nowadays systems require, in most cases, many complex FPGAs which are connected and interchange data and control between them in a robust and reliable way.
Not only the functionality of the system must be proved, but also its robustness, its functional behaviour under stress conditions by intensive tests to verify bandwidth tolerance, in order to provide the requested service to the highest standards.
To ensure the functionality of the design, its robustness, and to provide a way forward to quickly reproduce test cases, the verification of the FPGA and the system where it is instantiated is critical.
In modern systems, there is not a single optimized verification level that could be used to prove the correct implementation of the FPGA and the system. Different verification levels must be used in a divide-and-conquer approach, to ensure the quality of verification, so that later errors do not show up at the customer site during the final integration phase.
Complex FPGAs can be simulated only to a certain functional level in order to keep simulation time and testbench complexity as low as possible.
Simulation of complex FPGAs require as well the generation of testbenches that could be as complex as the design itself, with sufficient complexity to automate the generation of stimuli and checking of results, so that errors could be catched, in an automated way, as soon as they are produced, minimizing VHDL fix-and-simulate cycles duration, and saving development time.
The effort and complexity of simulating systems with many FPGAs grow exponentially in cost and in time, even with using modern verification methodologies like OSVVM, or UVM.
In order to be able to verify complex systems with a big number of FPGAs interconnected between them, reducing cost, reducing testbench complexity, reducing verification time, increasing functional coverage and maximazing results, it is necessary to look for other approaches.
One of these approaches is HW emulation on big and fast FPGAs. Traditionally HW emulation have been used to prototype big ASICs on a single, or many, FPGAs to demonstrate functionality before going to tapeout.
One of the environments used in AIRBUS CRISA during the last two years has been ProFPGA, a powerful HW emulation system, to verify complex FPGA systems, involving many FPGAs, as a way to do full system integration and verification, anticipating to integration errors, increasing functional coverage, speeding up verification, and ensuring functionality, robustness and quality of the FPGA and the system.
We will show how we used a powerful emulation system like ProFPGA has to emulate and interconnect a Power System Unit, composed by 32 FPGAs interconnected between them, to overcome the problems of the traditional verification methods by simulation, and how we were able to find and resolve tough issues, that would have been discovered very late in the integration process otherwise.
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