14–16 Mar 2023
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Presentations available

Continuous Integration in Space: An Approach to Automated Qualification of In-Orbit Experiments (Fraunhofer IIS)

16 Mar 2023, 12:05
25m
Erasmus High Bay (European Space Research and Technology Centre (ESTEC))

Erasmus High Bay

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Reconfiguration Reconfiguration

Speakers

Mr Moritz Schreiber (Fraunhofer IIS)Mrs Katja Vornberger (Fraunhofer IIS)

Description

With the Fraunhofer On-Board Processor (FOBP), we created a fully in-orbit reconfigurable FPGA experimentation platform in geostationary orbit which will launch in 2023 as part of the Heinrich Hertz satellite mission.
It provides digital signal processing for satellite communication for up to 450 MHz bandwidth and is flexibly programmable from ground.
Reconfiguring the two Virtex-5QV FPGAs changes the payload behaviour but clearance by the satellite operator is not necessary. Instead the involved parties demand exhaustive qualification before conducting the communication experiment. Additionally to testing the FPGA design in the target environment, the on-board software and its compatibility with the software-defined ground station has to be verified.
Continuous Integration (CI) provides the means to automate the necessary steps on ground. It not only reduces the required time to set up the measurement devices but also the risk of mistakes which could be made by human operators by ensuring reproducibility of the test results.

CI refers to the practice of regularly integrating code changes into a central repository, where automated tests are run to ensure that the code is stable and functioning properly. This practice was founded in the context of software development but can also be incorporated for automated tests on the target hardware for qualifying the target FPGA design and finally in-space deployment. This includes the integration of several devices like a power supply tester and a thermal vacuum chamber.
As the first step, the FPGA design is built from VHDL. Our fully automated buildsystem controls the Xilinx build tools. Each FPGA design is fully compatible to all FOBP models (on-ground reference and flight hardware). This ensures that the results of the tests can be applied to the model in space. Afterwards, the on-board software is built and tested for operation on an IP-based processing unit. FPGA design and software are then integrated into a single image.
The FOBP is able to receive design updates over the air through a custom in-band telemetry and telecommand link and reboots with upgraded firmware and software.
Additionally, a human readable report is generated, the runtime logbook for space components is supplemented and the resulting image is stored in the database of verified builds. This procedure is also applied for testing and upgrading ground station components like the software-defined radio modem.

With this approach to continuous integration in space, we have implemented proven methods for developing on-ground software and verifying space-grade FPGA designs including on-board software. This enables us to quickly and safely qualify novel experiments or even smaller updates for our Satellite Communication Laboratory in Space.

Primary authors

Mr Moritz Schreiber (Fraunhofer IIS) Mrs Katja Vornberger (Fraunhofer IIS)

Presentation materials