14–16 Mar 2023
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Presentations available

Practical and economic considerations for improving the reliability of FPGA-based control systems for space applications using a hybrid design approach (VORAGO Technologies)

15 Mar 2023, 11:10
30m
Erasmus High Bay (European Space Research and Technology Centre (ESTEC))

Erasmus High Bay

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Poster Session Poster Session

Speakers

Keith Odland (VORAGO Technologies) Germán Cuello (Vorago Technologies)

Description

Field Programmable Gate Arrays (FPGAs) are ideal single-chip solutions for many applications. Many of these applications find their way into space. By their very nature, they are re-configurable, enabling the designer to create a standard chassis that can be deployed for various missions.

Space-based applications pose a unique set of challenges not typically found in celestial implementations. Exposure to high levels of radiation and energetic particles is the most obvious. These particles change the properties of the gates contained in the integrated circuit (IC) and cause them to behave in unexpected and unpredictable ways. These changes can range from the flipping of a random bit in memory to the latch-up on critical circuitry, resulting in permanent and catastrophic damage to the system.

A common way to address these issues is to use radiation-hardened components in the system design. This applies to the FPGA and all other components, such as discrete logic, timing, power management, data acquisition, and communication. This is the most pragmatic and expensive way to mitigate the effects of ionizing radiation on the system. Components that are radiation hardened by design are typically two to three orders of magnitude more expensive than their industrial, common off-the-shelf (COTS) counterparts. In many space applications, this additional cost is prohibitive.

What if there was a way to increase the system's reliability significantly without increasing the cost proportionally?

Our approach uses a single radiation-hardened supervisor that monitors the FPGA for latch-up conditions. We report the results of validation work on VORAGO Technologies’ VA41630 in a 4-channel latch-up monitor configuration to mitigate latch-up on multiple devices in harsh environments. The proven results suggest that this device may replace custom discrete solutions and reduce required engineering and system characterization resources to speed up the design cycle.

This hybrid approach brings the best of both worlds. A design rugged enough for many space-based missions as well as cost-effective to enable scalable deployment.

Primary author

Keith Odland (VORAGO Technologies)

Co-authors

Dr Patrice Parris (VORAGO Technologies) Germán Cuello (Vorago Technologies)

Presentation materials