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Description
Although first introduced in 2005, the 65nm node still operates in the sweet spot of design complexity, performance, costs and applicability of aerospace grade ASICs. The DARE65T platform implements a complete library of digital and mixed signal IPs, that accommodate a Radiation Hardened By Design (RHBD) regular design flow and manufacture ASICs in commercial technology. To apply the right mitigation techniques against radiation effects, a test vehicle with technology components was characterized and irradiated under Total Ionizing Dose (TID). With two additional test vehicles, all developed IPs were characterized and irradiated under both TID and Single Event Effects (SEE) to confirm the mitigation techniques. Finally, a demonstrator ASIC was developed with Frontgrade Gaisler to confirm readiness of the libraries and integration views for making rad-hard components.
The measurements obtained from various test vehicles are used to calibrate SETstriker, a simulation tool that can identify Single Events Transient (SET) vulnerabilities at cell level.
Library design
For digital ASIC designs, the DARE65T platform includes 1.2V standard cell libraries that contain multi-Vt, multi-Lg and hardened cells. A 1.2V Single-port SRAM compiler allows for generation of any memory configuration, and 5 specific 1.2V Dual-port SRAM instances (0.5/1/4/8kx40b, 2kx24b) were designed. The IO offering includes multi-voltage programmable LVCMOS IO, LVDS (800 Mbps), SSTL15 (800 Mbps), SSTL18 IOs (800 Mbps) and a 96-bit DDR3 PHY hard macro block, where all IOs are cold-spare capable for redundant application. In addition, the platform provides several hardened mixed signal IPs: PLL (6.25 MHz–1.2 GHz), Bandgap-based current and voltage reference blocks (IVREF), current-steering digital-to-analog converter (IDAC), and a 1-ksps 10-bit on-chip temperature sensor.
Library test results
In this article we will address the technology components (NMOS, PMOS and BJT transistors, decoupling capacitors, resistors and diodes) and present the library validation results. No TID effects were observed for decoupling capacitors and diodes. For the unsalicided polysilicon resistor, the resistance drift was observed and explained for the first time. For the NMOS, PMOS and BJT transistors, parameters did drift as expected.
The results proved the IP robustness at least to 300 krad(SiO2) and no SEL observed during heavy ion tests up to 74 MeV∙cm2/mg (highest LET tested). The DARE65T platform provides a system designer with the variety of options needed to find the optimal solution from radiation hardness, fault tolerance, performance, area, and power consumption point of view: hardened (DICE-based flip-flops and clock-gating cells, C-elements, majority voters, etc.) and unhardened elements, threshold voltage options, etc.
Besides the standard cell and IP libraries, the platform users can access the SPICE-level SET striker software tool, fully compatible with the standard design flow. The tool allows for finding the sensitive area of the designed block and, in the case of redundant cells, indicating the sensitive pairs. Further layout analysis allows for improving the SEE robustness. For example, the DICE flip-flops use sensitive node spatial separation, and some weak points were found using the SET striker at the design stage. The heavy ion tests proved the robustness of the hardened flip-flops to an LET of at least 15 MeV∙cm2/mg, which is more than 10 times higher than the threshold LET of the previously reported unhardened devices and exceeds the maximum LET level of the high energy proton events.
With this information, the library cell design, and layouts were validated and considered ready for integration in a Demonstrator ASIC to also validate the integration views.
Demonstrator ASIC
Using the digital and mixed signal libraries, Frontgrade Gaisler designed a LEON5FT-based SoC named D65D (DARE65T Demonstrator). The architecture consists mainly of the following functional blocks and characteristics:
• 1x LEON5FT processor core with:
• Integer unit with 8-stage dual-issue pipeline.
• 4x4 KiB instruction and 4x4 KiB data L1 caches connected to a 128-bit multi-layer bus.
• Double-precision IEEE-754 floating point unit.
• Memory Management Unit (MMU).
• 128 KiB L2 cache, 512-bit cache line, 2-ways.
• 96-bit DDR2/3 SDRAM with Reed-Solomon EDAC.
• SpaceWire router with 4 external links.
• High-speed serial link SpaceFibre controller (no on-chip Serializer/Deserializer transceiver).
•x 10/100/1000 Mbit Ethernet interface.
• Other interfaces, such as MIL-STD-1553B (1x), CAN-FD (2x, with CANOpen support), UART (4x), SPI (2x), I2C (2x), GPIOs, FPGA
supervisor (GRSCRUB), SoC bridge, etc.
• Timers and watchdog.
• JTAG and Ethernet debug communication links.
• System frequency of 200 MHz.
Two test hardware setups were developed: one for functional and SEE testing and another for TID testing. A test software suite was also developed to exercise the SoC's main functional blocks.
Demonstrator test results
One heavy ion SEE test campaign and one TID test campaign were executed with the D65D.
The SEE testing was performed at the Radiation Effects Facility (RADEF) of the University of Jyväskylä (JYU), in Finland. The irradiation of three samples was in air using ion cocktails that allowed covering an effective Linear Energy Transfer (LET) range from 0.94 to 94.01 MeV∙cm2/mg at room temperature. The main results obtained were as follows:
• SEL immunity up to an LET of 94.1 MeV∙cm²/mg (tested with elevated temperature - ~100 ºC - and maximum supply voltages).
• SEU results collected with the device operating in dynamic mode in agreement with reference data from the DARE65T library. There is no evidence of error build-up in the D65D.
• Functional results (SEFI and SDC) obtained through the execution of multiple software test cases aimed at exercising the majority of the hardware blocks of the D65D.
The TID testing was performed at ESA’s ESTEC Co-60 facility, located in Noordwijk, The Netherlands. The irradiation of ten samples (five biased, five unbiased, and two reference samples) was performed with a dose rate of 0.426 krad(SiO2)/h from 0 to 100 krad(SiO2) and 2.170 krad(SiO2)/h from 100 to 300 krad(SiO2). No TID-induced failures were observed in any test sample at any test step. Additionally, no evidence of time-dependent effects was observed in any sample after the accelerated ageing test step regardless of the biasing mode. The results obtained reinforce the TID tolerance of 300 krad(SiO2) of the DARE65T library.
The final version of this work will present additional information about the test conditions and detailed results of the two irradiation campaigns (SEE and TID) performed with the D65D component, such as static and dynamic cross-sections obtained from the SEE tests.
