Speaker
Description
AI-based capabilities are increasingly enabling onboard satellite intelligence, but European solutions are currently limited to 28nm FDSOI technology, trailing US competitors like AMD's 7nm FinFET-based VERSAL. To close this gap, we present what is, to the best of our knowledge, the first radiation-hardened Coarse-Grained Reconfigurable Array (CGRA)-based hardware accelerator IP synthesised in 7nm UDSM technology — a landmark step for European space-grade computing. Built around a CGRA accelerator core, the architecture delivers energy-efficient, reconfigurable data processing capable of handling diverse AI and signal processing workloads under the strict power, reliability, and radiation constraints of satellite payloads.
The increasing complexity of space missions — spanning real-time Earth observation, in-orbit data analytics, and adaptive mission control — demands computing platforms that are simultaneously flexible, efficient, and radiation-hardened. CGRA-based accelerators are uniquely suited to this environment: their reconfigurability allows dynamic adaptation to evolving AI workloads, while their dataflow architecture minimises energy consumption compared to conventional processor-based solutions. Targeting 7nm UDSM technology further yields transformative improvements in transistor density and computational throughput over 28nm baselines, enabling a new class of onboard intelligence previously unachievable.
The same architectural advantages extend naturally to next-generation telecom applications. The growing computational demands of 5G and emerging 6G systems — including beamforming, regenerative payload processing and massive MIMO signal processing — impose strict latency, throughput, and energy constraints that CGRA-based designs are well positioned to meet. The insights gained from characterising and hardening this architecture at the 7nm node therefore carry broad relevance, contributing to Europe's strategic push for sovereignty in advanced-node IC design across both space and telecom domains.
In this poster, we provide an overview of the current hardware accelerator landscape for space applications, demonstrate the architectural advantages of our CGRA-based design for AI, telecom, and data processing workloads, and present quantitative performance, power, and area (PPA) synthesis results in TSMC's 7nm standard-cell library.