Speakers
Mr
Olivier Bernal
(ENSEEIHT/INP - LAAS/CNRS)Mrs
king wah wong
(CNRS - IRAP)
Description
The compact size and power consumption of the electron energy detector instrument IDEE TARANIS requires the use of a dedicated ASIC readout circuit instead of discret devices for energy measurement. The ASIC consists of 8 CdTe, 4 regular size Si and 1 small Si detectors readout. Each channel includes a charge amplifier, a shaper, a peak detector and an 8-bit ADC. Si type channel covers the energy detection range of 70keV up to 700keV while CdTe channel covers the 300keV to 4MeV range. For a 40-pF detector parasitic capacitances, low noise performances are achieved: 3120e- for Si type channels and 2335e- for CdTe type channels. Low power performance of 2mW at 650-kHz frequency per Si channel and 2.9mW at 40-kHz per CdTe channel is achieved. While both type of channel share a similar design, CdTe type channel analog front end had to include a pole zero cancellation in order to achieve the required frequency of operation. The ASIC has been tested in standalone as well as interfaced with the detectors. Finally, the ASIC has been qualified with a heavy ion test. The ASIC has been implemented in AMS 0.35µm HV CMOS technology.
Primary author
Mrs
king wah wong
(CNRS - IRAP)
Co-authors
Mr
Florent Bouyjou
(CEA)
Mr
Guillaume Orttner
(CNRS - IRAP)
Mrs
Hélène Tap
(ENSEEIHT/INP - LAAS/CNRS)
Mr
Jean-André Sauvaud
(CNRS - IRAP)
Mr
Olivier Bernal
(ENSEEIHT/INP - LAAS/CNRS)
Mr
Pierre Devoto
(CNRS - IRAP)
Mr
gilles roudil
(CNRS - IRAP)
Mr
marti bassas
(CNRS - IRAP)
Mr
olivier chassela
(CNRS - IRAP)
Mr
pierre-louis blelly
(CNRS - IRAP)
