AMICSA & DSP 2016

Scalable Sensor Data Processor: Architecture and Development Status

15 Jun 2016, 14:45

30m

Gothenburg, Sweden

Oral DSP Day: Rad-hard DSP chips and boards Session 1: Rad-Hard DSP Chips

Speaker

Mr Ricardo Pinto (Thales Alenia Space)

Description

Introduction ============ The Scalable Sensor Data Processor (SSDP) is a next generation on-board data processing mixed-signal ASIC, envisaged to be used in future scientific missions requiring high on-board processing capabilities. It offers a novel heterogeneous multicore architecture, combining two high-performance Xentium Digital Signal Processing (DSP) cores [1] together with a general-purpose LEON3FT processor [2], all served by a rich set of Input/Output (I/O) interfaces, including an on-chip Analogue-to-Digital Converter. The SSDP is envisaged to be used in future scientific missions like JUICE [3], easing the development and implementation of data processing functions, without neglecting the capabilities of control offered by the general-purpose processor. The main forces driving its design are processing power, power consumption and radiation tolerance. The focal point of these characteristics lies between flexibility and scalability, enabling the usage of the SSDP in missions with profiles so diverse as deep-space missions or planetary landers. The SSDP development is sustained by a consortium led by Thales Alenia Space España, and comprising Recore Systems, IMEC, Cobham Gaisler and Arquimea, bringing together expertise in the digital, analogue and mixed-signal domains. Such diverse expertise is of the utmost importance in order to tackle the technical challenges posed by integrating the many different components, yet achieving the proposed goals. Architecture ============ The SSDP aims at providing in a single chip all resources needed to perform several tasks pertaining to on-board data processing. Besides the state-of-the-art processing architecture, it has a diverse set of I/O interfaces for data acquisition, supporting external Analogue-to-Digital (ADC) and Digital-to-Analogue (DAC) converters, standardized interfaces like CAN, SPI, SpaceWire (SpW) and GPIO. It supports both high-speed and low-speed on-chip ADCs. These features enable a seamless integration with companion devices and external systems, both current and future. The SSDP architecture can be roughly divided into two major subsystems: Control, embodied by the Cobham Gaisler LEON3FT generic processor and its System-on-a-Chip (SoC) I/O interfaces; and Processing, embodied by Recore Systems Network-on-Chip (NoC) based multicore DSP subsystem, which provides two Xentium DSPs and its associated I/O interfaces. These control and processing subsystems are connected via a Bridge interface, enabling the exchange of data and signalling information between them e.g. interrupts. Despite this abstract subsystem division, the Control subsystem can also be used for processing tasks, thus exploiting the processing power of the LEON3FT processor and its I/O interfaces. Likewise, the Processing subsystem can be used to command interfaces on the Controlling subsystem. The ability of scaling the system was not neglected, and a Parallel Interface for chip-to-chip communication is included. This interface allows interconnection an SSDP to either another SSDP, an FPGA or other suitable device. This interconnection enables parallel data exchange with data-rates up to 800 Mbps, and includes flow-control mechanisms to ensure efficient communication. Control Subsystem ----------------- The control subsystem has a LEON3FT at its heart, supported by EEPROM and SRAM for application storage and execution. This is further enriched by typical I/O interfaces, such as SpW, CAN, UART, GPIO, SPI, and others. The SSDP Fault-Tolerant Memory Controller will support the emerging MRAM technology, which can be used instead of current EEPROM technologies. Time-keeping will be managed by the novel SpaceWire Time Distribution Protocol (SpW-TDP) [4], whose IP core will be enhanced to meet the SSDP time management requirements. The architecture of the Control system is intended to be highly compatible with the commercially available GR712 processor from Cobham Gaisler, thus enabling the reuse in the SSDP of code, tools and procedures already developed for the GR712. Processing Subsystem -------------------- The processing subsystem is powered by Recore Systems multicore DSP subsystem IP, which provides two Xentium DSPs, connected to local memories and peripherals via a highly performing NoC. The NoC has a 32-bit width, and it will work at system speed, thus yielding a maximum bidirectional throughput of 3.2 Gigabit per second. The storage of (volatile) data is performed through a rich hierarchy of memories, ranging from local high-speed tightly-coupled memories to external SDRAM at 100 MHz. Data acquisition can be performed via an external ADC, or using the on-chip fast ADC which supports sample rates between 20 Msps and 100 Msps. The configuration and exploitation of external ADC and DAC components will be possible from the Processing Subsystem, with sample rates up to 50 Mega-samples per second. Such devices can be configured via a serial bus like SPI or I2C. Development Status ================== The SSDP consortium encompasses several partners, with different domains of expertise: Recore Systems, providing the multicore DSP subsystem; IMEC, providing layout services, specific IP cores and the DARE cell library; Cobham Gaisler, with the LEON3FT subsystem; and Arquimea, with the on-chip fast ADC. The SSDP development will result in a CQFP mixed-signal ASIC, built in 180 nm DARE digital cell technology [5]. Engineering Models (EMs), Flight Models (FMs) and evaluation boards will be commercialized by Cobham Gaisler. The SRR was successfully closed out in October 2015, and the development is entering now its prototyping and validation stage, which will culminate with a PDR. For that, a prototyping board based on a Xilinx Kintex Ultrascale FPGA is being developed, which will provide enough FPGA resources to embed in a single chip both subsystems. This board will provide all the I/O interfaces needed by the SSDP, thus allowing their validation. The SSDP validation activities will be carried out with the help of a National Intruments PXI testbench comprising both hardware and LabView software. The SSDP will run software to support the validation procedures. Such a setup allows a simple yet powerful validation loop, which can be used at all levels of the validation procedures. References ================== [1] Recore Systems, Xentium® VLIW DSP IP Core - Product Brief, 2012. [2] Cobham Gaisler, GRLIB IP Core User's Manual, 2016. [3] European Space Agency, “JUICE Definition Study Report”, 2014. [4] Cobham Gaisler, “High Accuracy Time Synchronization over SpaceWire Networks”, 2013. [5] S. Redant, R. Marec, L. Baguena, E. Liegeon, J. Soucarre, B. Van Thielen, G. Beeckman, P. Ribeiro, A. Fernandez-Leon and B. Glass, “The Design Against Radiation Effects (DARE) Library,” in 5th Radiation Effects on Components and Systems Workshop (RADECS), Madrid, 2004.

Summary

Future science missions are envisaged to be demanding w.r.t. on-board data processing capabilities, due to the scarcity in downlink bandwidth together with the massive amount of data which can be generated by next-generation instruments, both in terms of data rate and volume. Therefore, new architectures for on-board data processing are in need.
The Scalable Sensor Data Processor (SSDP) is a next-generation mixed-signal ASIC aiming at fulfilling the processing needs of such missions, integrating in the same chip an heterogeneous multicore architecture, with two Digital Signal Processing (DSP) cores and a general purpose processor, together with Input/Output interfaces and data acquisition capabilities.

Presentation materials

Paper

1_1_SSDP_Architecture_and_Development_Status_20160613.pdf

Slides

1_1_P_SSDP_Architecture_and_Development_Status_20160614.pdf

summary

Conference_CV_R._Pinto.txt