Speaker
Mr
Hainan Liu
(Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA)
Description
Feitao Qi , Tao Liu , Hainan Liu , Chuanbin Zeng , Bo Li , Jiantou Gao , Gang Zhang , Fazhan Zhao , Jiajun Luo* , Zhengsheng Han , and Zhongli Liu
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA
Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences, Beijing 100029, CHINA
* Corresponding Author's Email: luojj@ime.ac.cn
In the harsh space environment, analog and mix-signal circuits would suffer drastic performance degradation due to radiation effects. A monolithic, high reliability pipelined analog-to-digital converter (ADC) with 10 bits resolution and 25MHz conversion rates is presented as a prototype exhibiting benefits from RHBP and RHBD approaches. The ADC prototypes are manufactured respectively by commercial 5V 0.35um bulk and rad-hard silicon-on-insulator (SOI) technologies. And both ADCs are tested in the same conditions for comparison.
The block diagram of the ADC prototype is illustrated as figure 1.
![Block diagram of the ADC prototype][1]
The micrographs of ADC in different technologies are shown in Figure 2, respectively.
![Micrographs of ADC in different technologies][2]
The rad-hard SOI CMOS technology adds silicon dioxide as a buried insulator layer upon silicon substrate as figure3. It provides CMOS a complete isolation between n-well and p-well, leading to the elimination of circuit latchup events. The technology is optimized and hardened to obtain excellent mitigation ability to radiation effects.
![Cross-section views of SOI and bulk CMOS technologies][3]
The bulk CMOS ADC is implemented with reasonable and rigorous layout rules, resulting in the immunity of SEL and SEFI up to 63 MeV•cm2/mg linear energy transfer (LET) during SEE experiment.
In order to improve the performance of anti-radiation, a suitable ADC structure is determined and designed; the current amplitude and capacitance value around certain sensitive parts are increased with special purposes. By implementing the above approaches and taking advantage of the inherent rad-hard SOI technology, the SOI-based ADC is capable of exhibiting much smaller deviations when radiated. Because most deviations could be corrected by ADC’s error correction logic with designed system redundancy, the SOI-based ADC acquires excellent rad-hard accomplishments. In contrast the bulk CMOS ADC with same schematic structure implementation could not be so efficient in experiments.
The regulated performance characteristic experiment indicates that both SOI ADC and bulk CMOS ADC could achieve effective number of bits (ENOB) of 9.5 bits, spurious-noise-free dynamic range (SFDR) of 72dB, differential non-linearity (DNL) of 0.4 LSB, and integral non-linearity (INL) of 0.5 LSB. The detail performance characteristics are listed in Table 1.
![Regulated performance characteristics of SOI-based ADC and bulk CMOS ADC][4]
The spectrums of SOI and bulk CMOS ADC are exhibited in figure 5.
![Spectrums of SOI and bulk CMOS ADC with a sampling speed of 25 MHz][5]
The total ionizing dose (TID) experiment reveals that SOI-based ADC achieves better TID tolerance, 300krad(Si), which nearly ten times higher than bulk ADC. The comparison of their TID responses is exhibited in figure 6.
![Comparison of TID responses between SOI and bulk CMOS ADC][6]
In the single event effect (SEE) experiment, both ADCs show immunities of single event latchup (SEL) and single event functional interrupt (SEFI) up to 63 MeV•cm2/mg LET. When LET is 17MeV•cm2/mg, the SOI-based ADC has a single event upset (SEU) cross-section of 3.1X10-6cm2/device, when LET is 63MeV•cm2/mg, the SOI-based ADC has a SEU cross-section of 9.6X10-6cm2/device, both lower than bulk ADC by two orders of magnitude. Figure 7 illustrates the differences of SEU cross-section between SOI and bulk CMOS ADC.
![Comparison of SEU cross-section between SOI and bulk CMOS ADC][7]
In conclusion, by taking advantage of rad-hard SOI technology along with RHBD approaches, the SOI-based ADC in space exhibits better performance with respect of SEE and TID over the one using commercial bulk CMOS technology.
[1]: http://img0.ph.126.net/VWFmLMmxyqPsmKYmCE2qmg==/6598074720343985115.jpg
[2]: http://img2.ph.126.net/RmwEafhqOBsTYn4u6UyxEw==/6598219855878851729.jpg
[3]: http://img1.ph.126.net/zg7jwdbTwOQOt5p9IzwY4Q==/6598140691041651067.jpg
[4]: http://img0.ph.126.net/Bt48wZ1dql3vXkHeD13IpQ==/6598083516436988703.jpg
[5]: http://img0.ph.126.net/wytmlqytiaqkvcuuWRzWWQ==/6598073620832357340.jpg
[6]: http://img1.ph.126.net/7k2AisugvvojSqHiDWqjEQ==/6631355837750306431.jpg
[7]: http://img2.ph.126.net/XW6aNnGO3c5F5vntrxHYZw==/6631261279750325570.jpg
Primary author
Ms
Feitao Qi
(Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA)
Co-authors
Mr
Bo Li
(Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA)
Mr
Hainan Liu
(Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA)
Mr
Jiajun Lou
(Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA)
Mr
tao Liu
(Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA)
