We present SIPHRA, an integrated circuit (IC) for the readout of single photon detectors, such as photomultiplier tubes (PMTs), silicon photomultipliers (SiPMs), and multi pixel photon counters (MPPCs). The circuit has been designed under contract from the European Space Agency (ESA) with support from the Norwegian Space Center and the University of Geneva. The ASIC requirements were derived from needs in Gamma-Ray Imaging, Polarimetry and Spectroscopy (GRIPS, [1]) and scintillating fibers for a gamma ray telescope (PANGU, [2]) and astro-particle missions (HERD, [3]). The circuit covers a wider range of technologies and applications in space and on Earth, for example, high-resolution gamma ray spectroscopy, detector front-end readout for diagnostic imaging in nuclear medicine, fast photon counting, and timing.
Figure 1 ![SIPHRA ASIC block diagram.][1]: Block diagram of SIPHRA ASIC.
The IC has 16 input channels and one summing channel (Figure 1): each channel can be used for pulse height spectroscopy and timing. The summing channel is important for the readout of detector arrays with monolithic scintillators. The programmable shaping time of 200 ns, 400 ns, 800 ns, or 1600 ns allows for pulse height spectroscopy with scintillators of various light decay properties. The current mode input stage (CMIS) is designed for large negative charge depending on the programmable attenuation (-16 nC, -8 nC, -4 nC, -0.4 nC) and accommodates relatively large capacitive load (several nF) and large leakage current (up to -100 μA from dark counts). Alternatively, CMIS can be by-passed to allow for positive charge depending on programmable gain (+40 pC, +4 pC, +0.4 pC). The IC contains one 12-bit analogue-to-digital converter (ADC) that allows for digitization of the pulse heights from all channels, including the summing channel at speed of 50 ksps maximum. Every channel output is available for external use and provides either the pulse height or a digital trigger/timing pulse. The programmable channel output facilitates many applications, such as, external waveform sampling and digitization, time spectroscopy, pulse counting, and triggering. The IC operates at 3.3-V supply voltage and dissipates about 15 mW without CMIS and 30 mW with CMIS. To save power, any channel or function can be programmed to power down. The ASIC has a serial peripheral interface (SPI) for programming its register settings and for relatively slow ADC data readout; faster readout up to 1Mbit/s is possible via serial data transmission line. All amplifier inputs are protected by diodes against over-voltage and electro-static discharge (ESD). The ASIC is designed in 0.35-μm CMOS process to be manufactured at a European foundry. We have manufactured test devices with the ADC, SPI, registers and buffers, and validated the design with respect to radiation. We measured a single-event-upset threshold of 50 MeVcm2/mg and we do not observe any latch-up up to the maximum tested energy of 135 MeVcm2/mg.
The ASIC design validation is scheduled for the summer 2016, using a custom-made test system (Figure 2, ![Block diagram of the ASIC test system.][2]). The test system is based on the Xilinx Zync-7000 system-on-chip and IDEAS custom-made firmware for the SIPHRA ASIC readout and control. The system is controlled via Ethernet from a standard computer. The SIPHRA ASIC is located on the ROIC test board, which allows one to connect to the detector array.
REFERENCES
[1] J. Greiner et al., “GRIPS Gamma-Ray Imaging, Polarimetry and Spectroscopy”, arXiv:1105.1265, see also http://www.grips-mission.eu
[2] Xin Wu et al., “PANGU: A High Resolution Gamma-ray Space Telescope”, arXiv:1407.0710v2, 17. Jul 2014.
[3] S. Zhang et al., "The High Energy cosmic-Radiation Detection (HERD) Facility onboard China's Future Space Station", arXiv:1407.4866 , 18. Jul 2014.
[1]: https://pbs.twimg.com/media/Ca8SkJ5UcAA-B9R.png:large
[2]: https://pbs.twimg.com/media/Ca8TP5WUMAA7eF0.jpg:large
