Digital Signal Processors (DSPs) have been popular devices for computation-intensive data processing for many decades. In comparison to General Purpose Processors (GPPs), their specific architectural designs support efficient processing of digital data via separate data and instruction memories, combined operations such as multiply-accumulate (MAC), hardware support for efficient loop execution, execution of multiple parallel operations (SIMD / VLIW), Direct Memory Access (DMA) mechanisms and other specific features. Ever increasing clock speeds and, more recently, many-core designs have led to significant performance increases, a trend that is still continuing.
In parallel, programmable logic devices (PLDs) have seen a dramatic evolution in terms of performances, popularity and capabilities of programming tools. Originally starting from relatively modest complexity level that allowed the implementation of glue logic and other specific circuitry, the recent generation of programmable devices, in the form of memory based Field Programmable Gate Arrays (FPGAs), allows not only to complement dedicated Application Specific Integrated Circuits (ASICs) including GPPs and DSPs, but can replace them entirely in many application cases.
The application spectrum for programmable devices with respect to GPPs and DSPs has therefore evolved from a complementary, supportive role to a more competitive/ synergetic one.
In the commercial world, a next step – the integration of FPGA and GPP / DSP – is already taking place [1, 2, 3]. After the integration of hard macro processors in available commercial FPGAs, large processor manufacturers are integrating FPGA dies or -fabric in their high performance processors for purposes such as programmable functionality extensions like application specific co-processor implementations [4] .
It is common knowledge that commercial processor technology trends are arriving in the space processor technology area with a typical delay of 10-15 years. Therefore it is reasonable to assume that the integration of processors / DSPs and FPGAs on the same chip is about to arrive in qualified space ASICs around 2020, probably first in the form of Multi-Chip Modules (MCMs) or in FPGAs with integrated processor macros, and – possibly some years later - followed by DSPs and processors with integrated FPGA fabric. This paper will focus on the integration of FPGA fabric in future DSP Systems on Chip (SoCs).
Already today, the advantages of integrated FPGA fabric on space qualified DSP chips are obvious.
Many application cases require the combination of processor chips with separate ADC, DAC, analogue frontend chips, specific interface chips, and specific co-processors. The necessary glue logic is typically provided via a separate, suitably sized FPGA. Integration of glue logic in FPGA on the processor chip allows to reduce the component count and cost, saves printed circuit board area and mass, increases reliability, lowers power consumption, and ensures the same level of radiation hardness for processor and logic. Additional use cases of similar complexity could be the on-chip FPGA implementation of specific interface types, related protocols, and similar functionality.
Another application area, requiring more capable FPGA fabric, is the on-chip implementation of co-processor or pre-processor functions. This might range from simple functions like specific data operations or an FIR / FFT accelerator to FPGA based data compression algorithms or even the integration of full-fledged software programmable VLIW DSP IP cores, in all cases possibly combined with additional logic and interlinks as required by the specific application case.
Finally, the integration of FPGA fabric in the heart of a processor core can allow the implementation of specific instructions that may speed up particular type of processor operations significantly.
For the integration of FPGA fabric on digital processors, specifically future many-core space DSPs, there are multiple options. An FPGA can be integrated as a separate die in a MCM, or with the processor cores on the same die. For MCM designs, dies exist from several companies. For on-die integration, both fully synthesizable e-FPGA designs as well as full-custom high density FPGA IP are available from European and other sources. A large trade space exists for the number, size, type and complexity of FPGA tiles on a digital chip. Both SRAM based and Flash memory based designs are available, with some specific restrictions to ASIC processes. The integration of analogue / mixed signal design elements on the same chip represents an additional dimension in the design space; also here, restrictions to ASIC processes and available IP apply.
