Speaker
Mr
Jan Steinkamp
(IMST GmbH)
Description
A fast and reliable development of a Rad Hard Space product benefits on a dynamic and efficient way of an ASIC design and supply chain. Design and qualification of a new ASIC is associated with a long development phase. Using an ESCC qualified IP library for the ASIC can reduce this development phase significantly and lowers the costs of the product. This supply chain resolves the trade-off between a full custom design with all associated qualification steps and a semi optimized product based on standard ICs.
IMST and TESAT Spacecom are currently working in a DLR funded R&D project to built up such an ASIC supply chain that will be offered by IMST after approval by ESCC consortium. Completion of this project is planned for Q1 2017.
A first publication of this ASIC supply chain establishment has been given on the AMICSA 2014 in CERN with the title: 180nm CMOS Mixed-Signal Radiation Hard Library as base for a full ASIC supply chain
Now an update will be given on the current status of this project with measurement results including TID and SEE evaluation. The designed Library elements will be presented and an overview of the supply chain will be given with all supported technology features, package choices and the design flow information.
The radiation hardened library designed by IMST, called HARD Library (HARD= Hard Against Radiation Design) is built on the XH018 180 nm CMOS technology from XFAB. It supports I/O cells for 3.3 V and 5 V supply as well as level shifter I/Os for a negative supply voltage of -5 V on the ASIC. The other IPs are specified with the intention to cover a wide range of applications. The IP library contains data converters, biasing cells, memory modules, a reconfigurable opamp, LVDS driver and receiver, SPI interface, OTP cells, clk PLL, oscillators and special I/Os with cold spare functionality.
A ceramic quad lead frame package family has been developed for the supply chain with different pin counts from 32 up to 256, supporting die sizes from 1.5 X 1.5 mm^2 for the smallest package up to 10 X 10 mm^2 for the largest package.
Two main design flows are targeted: One is a turn-key design by IMST based on customer requirements, while the other flow assists a co-design with the customer where the customer is allowed to provide encrypted VHDL codes. In the latter case IMST is creating the netlist with selected digital standard cells and implements TMR structures in order to guaranty a Rad Hard design. Analog features are handled by IMST using the IP library. On either case IMST delivers a tested, qualified and assembled Rad Hard ASIC.
Primary author
Mr
Jan Steinkamp
(IMST GmbH)
Co-authors
Mr
Frank Henkel
(IMST GmbH)
Mr
Volker Lück
(Tesat Spacecom)
