Speaker
Mr
Staf Verhaegen
(imec)
Description
DARE180U is a radiation hardened system-on-a-chip (SoC) design platform including mixed-signal and full-custom analogue circuits. It is built on the commercial UMC L180 MM/RF 1.8V/3.3V, Single Poly 6 Metal (1P6M), P-Sub/Twin-Well CMOS technology. In order to facilitate full custom radiation aware analogue design an analog design kit (ADK) is provided.
From the start this ADK targeted total-ionizing-dose (TID) requirements up to 1 Mrad. The ADK provided enclosed layout transistor support (ELT) with W/L design documentation, Cadence virtuoso pcells and an adapted layout-versus-schematic (LVS) check. Based on literature the effect of the ELT shape on the device performance can be taken into account during design phase and, by using the pcell, the layout phase can be sped up. Additionally an optional verification check is provided for well and substrate density to mitigate single-event latch-up (SEL).
Over the years radiation measurement results on TID, SEU, SET and SEL have been gathered. This included measurements on test vehicles using specifically designed test structures including single devices and digital or analog building blocks, but also data from radiation tests on SoC prototypes. For the design of the test vehicles always a trade-off has to be made between budget for test structure design and (radiation) measurement and the extra gained knowledge. The results of the measurement campaign are not always fully conforming to the expectation and in that case the data post-processing has to be adapted to still derive as much information usable by an analog radiation aware designer.
The provided ADK is developed to fulfill several needs of the analog designer. First of all it should be a natural extension of the provided foundry PDK and should reuse the knowledge already in there and not reinvent the wheel. The ADK should also fit perfectly in the design environment already used by the customer and be adaptable to the customer’s internal flow. Recent versions of the Cadence Spectre device simulator help the designer by giving warnings for suspicious circuits and models. To avoid warning blindness the ADK should avoid introducing warnings itself. As radiation hardness requirements are dependent on the targeted radiation environment of the final chip, the ADK should help in optimizing for this but at same time prevent the situation for worst-case overdesign as much as possible.
Based on the available measurements and the given requirements the ADK has been extended with:
- Fine-tuning the modeling of the effect of the shape of the ELT on the
drive strength of the device.
- Improved asymmetric parasitic modeling of the ELTs in the Spectre models as normal BSIM and other models assume straight devices and thus an equal length for the gate to the source and to the drain overlap.
- Additional TID process corners in the Spectre models so design can be optimized for
different radiation environments
- Custom Virtuoso schematic checks to indicate to the designer the presence of radiation sensitive devices during the design phase (e.g. already before layout)
- More extensive support of Virtuoso Layout XL features by the pcell
In the paper these extensions will be discussed more in-depth together with the measurement data on which these extensions were based.
Primary author
Mr
Staf Verhaegen
(imec)
