Speaker
Dr
Rajan Bedi
(Spacechips Ltd.)
Description
Today, the cost and effort to develop satellite payloads has to be repeated for almost every new mission, introducing unnecessary re-design, re-test, performance, re-qualification, schedule and budget risks to key programs.
Operators are constantly complaining to OEMs that the cost to develop satellites is prohibitively expensive, delivery takes too long and never right-first-time, while satellite manufacturers are handicapped by the limitations of current space electronics.
Digital telecommunication payloads have become handicapped by traditional mixed-signal convertor technology: high I/O counts, large packages introducing parasitics which limit performance, complex layout and routing constraints adding to design effort and resulting in more expensive PCB fabrication, as well as the power requirements of ADCs/DACs. The current approach of developing flexible, space electronics is simply too bespoke, too expensive, too inflexible and too power consuming to deliver tomorrow's, space-enabled world for everyone.
For example, the Alphasat telecommunication payload, the Sentinel Earth-observation satellite and the NovaSAR mission used 10, 8 and 12-bit ADCs respectively from the same supplier. In terms of on-board processing, the overall function of each transponder was similar, however, because each of the three missions had individual systems requirements, the mixed-signal technology that was available then necessitated the development of three, unique, avionic sub-systems triplicating effort and cost.
The Alphasat and recently announced Inmarsat 6 telecommunication payloads both use ADCs from the same supplier, however, the latter uses 90 nm ASIC technology while the former uses 0.18 µm. In terms of on-board processing, the overall function of each channelizing transponder is identical, however, because both missions have individual systems requirements, two unique avionic sub-systems have had to be developed doubling effort and cost.
For the first time, JESD204B, serial-I/O ADCs and DACs offer manufacturers of satellite sub-systems the possibility to continually deliver bespoke and improved levels of performance to telecommunication operators without having to re-engineer the avionics hardware. Non-recurring, design effort and costs will significantly reduce while recurring manufacturing and test costs will also decrease, allowing future satellites to be delivered right-first-time, within budget and to schedule. This innovation represents a profound advance in payload design and a hugely enabling and disruptive step-change for the satellite industry!
Regardless of the SNR performance (resolution) required by individual operators, the digital interface will always remain the same thus avoiding the need to re-design and re-qualify hardware sub-systems. Only the FPGA configuration will need to be updated to reflect larger word lengths allowing future satellites to be delivered right-first-time, within budget and to schedule.
To promote the new architectural concept, the paper will also propose device-level pin-outs to ensure a scalable roadmap which will allow operators to avail of bespoke and increasing performance without the need for OEMs to continually re-engineer the avionics hardware.
Primary author
Dr
Rajan Bedi
(Spacechips Ltd.)
