Speaker
Dr
Francesco Piazza
(Saphyrion)
Description
Saphyrion Sagl is developing under an ESA contract a new chip-set for L-band radiometer applications, which consists of an RF down-converter and a latched comparator (1-bit AD-converter). The chip-set is being developed in collaboration with MIER Comunicaciones, who will use it on their next generation of radiometers. At present fully operating ASIC prototypes are available and are being characterized.
The RF ASIC is a single conversion superheterodyne receiver, which contains a programmable gain LNA (2 different gains), a double-balanced active RF mixer with active input signal coupler, an IF-strip comprising digitally programmable gain stages (PGAs) and a VCA stage, and an IF output buffer with power measurement amplifier. The RF chip will be encapsulated in a ceramic-metal 36 pin QFN package. The companion AD-converter ASIC - called DADC - is a 130MHz dual-channel latched comparator with direct and multiplexed outputs. It will be encapsulated in a 16 pin QFN package, also of ceramic-metal design. The new chip-set is designed to be radiation tolerant, making use of the design techniques that Saphyrion developed for its GNSS front-end chip-set consisting of SY1007 (RF down-converter) and SY1017C (ADC/DAC and interface ASIC).
In this presentation the architecture of the new chip-set and the radiometer including it, as well as the design choices and trade-offs, will be presented, followed with some circuit details. Results from the electrical characterization will be presented next. As a conclusion the remaining steps towards industrialization and space qualification to ESCC9000 of the chip-set will be shown, together with the planned road-map.
Primary author
Dr
Francesco Piazza
(Saphyrion)
Co-authors
Mr
Angelo Consoli
(Saphyrion)
Mr
Roberto Materni
(Saphyrion)
