Speaker
Dr
Constantin Papadas
(ISD)
Description
We present a current-steering, low-noise, radiation hardened Digital-to-Analog
converter, optimized to operate in the frequency range between DC and 50kHz. The
DAC receives 24-bit sampled data in a synchronous serial format and converts it into
a differential current analog signal. It uses a third-order multi-bit Sigma-Delta
modulator, which provides superior noise and linearity performance. The embedded
interpolator follows a multiple-stage architecture and consists of an FIR equiripple
low-pass filter followed by two cascaded stages of Half-band equiripple filters. The
last stage is a programmable SINC filter, which provides variable interpolation ratios
allowing sampling rates as high as 310kHz. The system operates on a single clock
domain, which is provided externally. The output current matrix features a Return-to-
Zero (RTZ) technique to improve the linearity by ensuring that each elementary
current source is zeroed, regardless the data value of the sample sequence. The DAC
is implemented in a rad-hard 150nm CMOS-SOI process, exhibits an SNR figure of
better than 108dB, and consumes 62mW of power.
Primary author
Makis Karaolis
(ISD)
Co-authors
Mr
A. Stafylidis
(ISD)
Mr
Boris Glass
(ESA)
Dr
Constantin Papadas
(ISD)
D. Fragopoulos
(ISD)
Kostas Makris
(ISD)
