SERESSA International School 12-16 Nov. 2018

Session

Mitigation and Hardening

12 Nov 2018, 17:00

Newton 1-2 (ESA/ESTEC)

10. EEE Parts in the New Space Paradigm

Mr Kenneth LaBel (NASA-GSFC)

12/11/2018, 17:00

Mitigation and hardening

As the space business rapidly evolves to accommodate a lower cost model of development and operation via concepts such as commercial space and small spacecraft (aka, CubeSats and swarms), traditional EEE parts screening and qualification methods are being scrutinized under a risk reward trade space. In this presentation, two basic concepts will be discussed: The movement from complete risk...

16. Radiation Effects Hardness Assurance for space mission

Dr Stephen Buchner (United States Naval Research Laboratory)

13/11/2018, 09:30

Mitigation and hardening

The approach used to ensure that parts will meet performance requirements for a mission operating in a radiation environment will be discussed. First part
will mostly focus on Single Event Effect Hardness Assurance. A particular mission will be used to illustrate the method. Second part will develop total ionizing dose (TID) and displacement damage (DD) hardness assurance.
Rationale for...

17. System Hardening and Real Applications

Mr Michel Pignol (CNES)

13/11/2018, 11:00

Mitigation and hardening

This talk describes the suitable protections at architecture and system level against the effects of radiation on electronic components and digital systems. After the description of the general architecture of a space avionics system, the potential solutions for each type of units constituting an on-board computer are presented through the example of real space applications: avionics bus,...

4. Mitigation in ASICs and FPGAs

Mr Agustin Fernandez-Leon (ESA/ESTEC)

14/11/2018, 09:30

Mitigation and hardening

19. New Developments in FPGA: SEUs and Fail-Safe Strategies

Mrs Melanie Berg (NASA - GSFC)

14/11/2018, 11:00

Mitigation and hardening

Technology is changing at a fast pace. Transistor geometries are getting smaller, voltage thresholds are getting lower, design complexity is exponentially increasing, and user options are expanding. Consequently, reliable insertion of error detection and correction (EDAC) circuitry has become relatively challenging. As a response, a variety of mitigation techniques are being implemented. They...

28. Development of a Hardened 150nm Standard Cell library

Joao Baptista dos Santos (Santa Maria Design House)

14/11/2018, 12:00

Mitigation and hardening

The effects produced by radiation on integrated circuits can be classified into Single Event Effects (SEE) related to transient problems and Total Ionization Dose (TID) effects that arise due to the long exposure time ionizing radiation. The mitigation of these effects on integrated circuits can be done in three ways: Manufacturing Process Level, Architectural Level (redundancy) and Layout...

29. Automotive safety challenges based on AEC Q100 / ISO 26262 requirement

Sung Chung (QRT Inc.)

15/11/2018, 11:00

Mitigation and hardening

20. New Paradigm of error correction used for reliable embedded memories in aerospace applications

Dr Fakhreddine Ghaffari (ENSEA)

15/11/2018, 12:00

Mitigation and hardening

30. Solar Cells

Dr José Ramón González (ESA/ESTEC), Dr Carsten Baur (ESA/ESTEC)

15/11/2018, 14:30

Mitigation and hardening

39. Development of read-out interfaces for pixel particle detector Timepix

Milan Malich

Mitigation and hardening

Poster

Development of read-out interfaces dedicated for the advanced hybrid radiation pixel detector Timepix will be presented. A basic concept and importance of a read-out interface as an absolutely necessary supporting electronics for proper operation and exploitation of the radiation detector Timepix and its advanced features will be explained. Then several application specific variants of...

45. On-membrane PD SOI MOSFET with micro-heater for TID in-situ annealing: experiments versus Eldo and Atlas simulations.

Mr Sedki Amor (Institute of Information and Communication Technologies, Electronics and Applied Mathematics, Université catholique de Louvain, Place du Levant, 3, 1348 Louvain-la-Neuve, Belgium.)

Mitigation and hardening

Poster

Abstract: Silicon On Insulator (SOI) technology has already improved immunity to Single Event Effects (SEE) thanks to the presence of the Buried Oxide (BOX). However, this technology remain very sensitive to the Total Ionizing Dose (TID) [1]. In recent works, we have integrated micro-heaters in the close vicinity of Partially-Depleted (PD) Metal-Oxide-Semiconductor Field-Effect Transistors...