Open Source VHDL Verification Methodology (OSVVM) is an advanced verification methodology and library that simplifies the creation of structured, transaction-based tests and test environments that are powerful enough for ASIC verification, yet simple enough for small FPGA verification.
OSVVM is implemented as two separate open source libraries: OSVVM Utility Library and OSVVM Verification IP Library. Currently these are hosted on GitHub. With the IEEE 1076-2019 standardization effort, the 1076 packages are now IEEE Open Source. Following the path of IEEE 1076, OSVVM has been accepted as an IEEE Open Source project and will be migrating the primary Git repository to the IEEE hosted site sometime in Q1 2020.
OSVVM was named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study.  In Europe, VHDL is used in 78% of all FPGA designs and OSVVM is used by 30% of the FPGA Verification teams – SystemVerilog and UVM is only used by 20% of the FPGA Verification teams.
The OSVVM Utility Library uses a set of packages to create features that rival language based implementations (such as SystemVerilog and UVM) in both conciseness, simplicity, and capability. This presentation provides an overview of OSVVM's capabilities, including:
• Transaction-Based Modeling
• Constrained Random test generation
• Functional Coverage with an API for UCIS coverage database integration
• Intelligent Coverage Random test generation
• Utilities for testbench process synchronization
• Utilities for clock and reset generation
• Transcript files
• Self-Checking – Alerts and Affirmations
• Message filtering – Logs
• Scoreboards and FIFOs (data structures for verification)
• Memory models
The OSVVM Verification IP Library is a growing set of transaction based models. Currently the repository has models and testbenches for
• AXI4 Lite: Master and Slave
• AXI Stream: Master and Slave
• UART: Transmitter and Receiver
Looking to improve your VHDL FPGA verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them.