17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

Accelerating the Journey from C/C++ to Hardware

18 Mar 2020, 12:40
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Design Flow Design Flow


Mr Pantelis Sarais (Silexica)


High-Level Synthesis (HLS) methodologies is proposed since around 15 years as a promising design methodology. Nevertheless, software engineers are still not able to get the maximum benefit from HLS due to the required knowledge about both parallelism and the specific FPGA hardware architecture. This presentation will explore the common design challenges engineers face when using HLS and how SLX for FPGA helps engineers to overcome them.

Some of the challenges include applications that make extensive use of non-synthesizable and hardware unfriendly code, identifying parallelism and when and where to insert pragmas.

SLX for FPGA is a programming tool that analyzes C/C++ code to provide a deep understanding of software interdependencies, parallelization opportunities and to enable an automatic design optimization and pragma insertion.

Primary author

Mr Pantelis Sarais (Silexica)

Presentation Materials