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Description
The DARE65T platform is an analog/mixed signal RAD-hard platform based on TSMC 65nm RF/LP technology. It includes an extensive variety of library cells like standard cells, IO, Single and Double Port RAM, PLL, ADC and DAC, bringing the first advanced node sibling to the DARE platform family.
This paper introduces a test vehicle, developed to validate functionality, perform electrical characterization and ultimately perform irradiation testing (SEE and TID) to confirm the radiation hardening techniques applied during the library design phase.
The test vehicle contains test circuits to allow for analysis of TID effects on standard technology devices, and circuits for validation, characterization and irradiation testing of the library cells, both in SEE and TID.
Electrical validation and characterization includes the parameter measurement of every device and library cell. For TID, parameter drift up to 300kRAD was measured before, during and after the campaign while the supply current of many individual power domains was monitored accurately, according to ESCC standard TID specifications. In SEE, heavy ion particle strike effects were monitored for all library cells to confirm critical threshold and cross-section figures over a range up to 65MeV·cm2/mg for SET and SEU effects, and up to 75MeV·cm2/mg for SEL effects, complying with ESCC SEE standard specifications. Also here, individual power domains were monitored accurately. To get a detailed understanding of SEE impact on the standard cells, specific test structures were developed that allow for 10ms periodic sampling and capturing radiation effects, reducing the risk of multiple heavy ions affecting the same cell to less than 5% while reaching a total fluence of at least 1e7 particles/cm2. In total 98 standard cell variations were selected (gate length 60 and 70nm, Vt threshold LVT/SVT/HVT and drive strength up to x16) each reaching up to 1000μm2 sensitive area, to guarantee sufficient statistical relevance on the final test data. These circuits allow for counting the number and measure the duration of SEE effects. For each of the analog/mixed signal library cells a dedicated test circuit was designed to detect SEE effects. These cells and circuits were instantiated 1 or 2 times only, as their sensitive area is much smaller with respect to the physical area, so SEE analysis was restricted to specific parameters only.
The die was assembled in a CPGA-256 package, which is among the highest pin count standard packages generally available. Nevertheless, as the number of digital control and monitoring pins to all test structures and library cells goes far over 1000, a pin multiplexing strategy was implemented with a radiation hardened SPI interface. A regular production tester was employed to operate the digital pins through the SPI interface every 10ms.
In parallel, it stimulates and measures the analog signal and supply pins directly connected to all analog blocks. Oscilloscopes were used to acquire waveforms of various analog interfaces and to detect SET pulses propagating from silicon to PCB.
In total over SEE 90 runs were performed for 3 samples, 6 LET levels and 5 test cases in the course of 3 days.
The acquired test data for validation, characterization and irradiation are currently being analyzed and test results, along with final platform specifications, will be available by the end of April.
