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Description
The DARE22G Phase-Locked Loop (PLL) has been designed in a 22nm Fully Depleted Silicon On Insulator (FD-SOI). It is required to be not only a radiation-hardened, but also low jitter PLL, with a target period jitter of less than 1ps for a 3GHz output frequency. As the application of the DARE22G PLL is in a digital system, period jitter is selected as a requirement in this design, instead of absolute jitter and cycle-to-cycle jitter. In the DARE22G PLL, the maximum output frequency of the loop itself - composed of a Voltage-Controlled Oscillator (VCO) based on a ring oscillator, a programmable Charge-Pump (CP) synchronized with a loop divider, a Phase Frequency Detector (PFD), Feedback Divider (FDIV) and a 2nd order Low Pass Filter (LPF) - is 3GHz, and two frequency dividers are connected to the output of the loop in series. They are called ODIV1 and ODIV2. If the division factors of ODIV1 and ODIV2 are set to 1, the DARE22G PLL output frequency is 3GHz.
The test structure for the jitter measurement is simply one test buffer connected to the output of the DARE22G PLL. The test buffer is an inverter with high driving strength and decoupling capacitors to suppress supply noise. Since the high inductance of the bond wires easily attenuates and corrupts high frequency signals, it is essential to minimize the inductance of the bond wires. For this purpose, firstly, three pads are connected to the test buffer output to implement three bond wires in parallel. Secondly, the bond wires on the silicon chip are directly landed on the test board without a package.
In the theory of PLL design, the input clock frequency and the division factor of the output dividers (ODIV1 and ODIV2) must have no impact on the period jitter (rms value) of the PLL output clocks. We measured the period jitter for 30 configurations, which are combinations of the input clock, FDIV, ODIV1, and ODIV2, to confirm the theory. Configuration A-1 has an input clock of 23.4375MHz, a division factor of FDIV=128, and division factors of ODIV1=1, and ODIV2=1, 2, 4, 8, 16, 32, 64, 128. The input clock of 23.4375MHz is the minimum required for the DARE22G PLL to create 3GHz output clock. In Configuration A-2, the input clock frequency and FDIV’s division factor are the same as in Configuration A-1, with the only difference being the division factors ODIV1=2 and ODIV2=1, 2, 4, 8, 16, 32, 64. Configuration B-1 has an input clock of 100MHz, a division factor of the FDIV=30, and the same division factor for the output dividers (ODIV1 and ODIV2) as Configuration A-1. The input clock of 100MHz is the maximum input clock that the DARE22G PLL can use to create a 3GHz output clock. Configuration B-2 has the same input clock frequency and the FDIV division factor as Configuration B-1, with division factors for the output dividers (ODIV1 and ODIV2) the same as Configuration A-2. These configurations are controlled by a Serial Peripheral Interface (SPI) implemented in the test vehicle.
The test instruments used include the Keysight N6704B power supply, R&S SMA100B signal generator, R&S RTP084 high performance oscilloscope (Bandwidth 16GHz), and Digilent Digital Discovery pattern generator as a SPI controller.
During the measurement, the DARE22G PLL operated with a 0.8V nominal supply voltage at room temperature. As a result, it has been confirmed that the input clock frequency and the division factor of the output dividers (ODIV1 and ODIV2) have no impact on the period jitter (rms value) of the PLL output clocks, as the measured period jitter shows consistency for all configurations. In conclusion, the DARE22G PLL’s period jitter (rms value) is 0.6 picosecond for a 3GHz output clock frequency.
