Speaker
Mr
Olivier NOTEBAERT
(Airbus Defence and Space)
Description
The use of COTS based computers for high performance digital processing in space application is an alternative to fully space-grade systems. Indeed, state of the art commercial processing devices achieve significantly higher performance than space-grade devices but generally do not fulfil space mission’s expectations mainly in term of radiation tolerance and thermal dissipation. However, within a system surrounded by space-grade devices and software for monitoring and control, such devices may deliver extreme processing performance with an overall level of reliability and availability which is fully acceptable for a given mission.
Within the framework of ESA TRP/GSTP studies devoted to the development of High Performance COTS Based Computers (HiP-CBC) in space applications, a generic architecture has been defined by Airbus Defence and Space to efficiently mitigate the erratic behaviour of commercial grade processing devices such as DSPs, general purpose micro-processors or FPGAs when they are submitted to the space radiation environment. Functions for detection and management of the sporadic errors induced by the radiation effects are developed with standard space-grade device - called SmartIO - interfacing with one or several high performance data processing boards implemented with commercial processing devices. A TRL 5/6 prototype implementation with a SmartIO based on a SCOC3 component (SCOC3 is a Spacecraft Controller on a Chip including a LEON3 processor with several interfaces such as 1553, CAN bus, and SpaceWire) and COTS based processing board made around Texas Instrument TMS320C6727 DSPs has been designed and manufactured within the frame of this ESA project. This demonstrator has validated the concept and the maturity of the so called Generation 1 of SmartIO (i.e. based on fully mature 2015 existing technologies) which remains limited to the coverage of applications with moderate needs in term of data processing due to the limited bandwidth of SpaceWire (~200 Mbps) and processing performance of the SCOC3 (80 MIPS). Higher rates will be required for e.g. on-board image, radar or telecom signal processing with a support of serial links in the 1-10 Gbps range such as Serial RapidIO or the SpaceFibre currently in development.
For example, Machine-to-Machine (M2M) communications, serving the broader Internet-of-Things (IoT), are receiving increasing interest. They have a very large market and growth potential, with increasing needs in the low-cost, low data rate segment. Complementing the ground networking through satellites is the only solution to provide global continuous coverage, with growing interest in low altitude satellite constellations embarking Software Defined Radio (SDR) payloads. However, current space technologies are not adequate to offer a competitive solution for commercial services with a satisfactory level of quality of service. To be commercially successful, flexible and regenerative payloads, delivering very high performances under severe cost, size, and energy constraints are mandatory. This is where the HiP-CBC concept and its SmartIO comes in; “enabling access” to the processing performances of latest COTS components based on more power efficient silicon technologies, which is identified as the most promising strategy. Many other applications related for instance to data collection, spectrum survey or air-traffic control could benefit of such development.
Exploring this promising technical path, Airbus Defence and Space is currently working on an innovative architecture of a generic Radio-Digital Processing Module (R-DSP) based on COTS components with the Generation 2 of the SmartIO with support of ESA through an ARTES program. For that purpose, commercial SRAM FPGAs have been selected to implement the high processing layer of the R-DSP, able to deliver a theoretical capacity of at least 50 GMAC/s to fulfil various mission needs. The implementation of the SmartIO function has been extended to a rad-hard anti-fuse FPGA, which provides a sufficient number of I/O pins and bandwidth capacity to interconnect a multi-port RF front-end with several mitigated commercial FPGAs. A SpaceWire link is also included in the design to provide a standard interface between the SmartIO and the rest of the payload network. The resulting architecture is modular and can be easily adapted to implement Triple Modular Redundancy (TMR) or Dual Modular Redundancy (DMR) macro-mitigation techniques, according to the availability requirements of the target mission.
Summary
Architectural solutions for improving robustness of space computers w.r.t. radiations effects enables the development of high performance computers based on commercial grade digital processing devices. The ESA study HiP-CBC (High Performance COTS Based Computer) has validated the radiation mitigation concept with a TRL6 DSP demonstrator. This concept is now being applied for a new range of payload processing applications such as digital signal processing on regenerative telecom mission.
Primary authors
Dr
Lyonel Barthe
(Airbus Defence and Space)
Mr
Olivier NOTEBAERT
(Airbus Defence and Space)
Co-authors
Mr
Jean-Luc Vanhove
(Airbus Defence and Space)
Mr
Olivier Prieur
(Airbus Defence and Space)
