May 31, 2022 to June 3, 2022
Círculo de Bellas Artes of Madrid
Europe/Madrid timezone

Implementation and Evaluation of Sum-Int ADC IP-core on NanoXplore FPGA

Jun 3, 2022, 10:30 AM
Círculo de Bellas Artes of Madrid

Círculo de Bellas Artes of Madrid

42, Alcala Street 28014 Madrid
Analogue intellectual property and re-usability of analogue circuits in space Analogue intellectual property and re-usability of analogue circuits in space


Mr Pavel Pisa (PiKRON s.r.o.)


The Summa-Integration analog to digital conversion principle is used for decades in PiKRON's company designed liquid chromatography spectrophotometric detectors as well as for winding currents sensing in permanent magnets synchronous motors and stepper motors control units. The principle has been implemented into a NanoXplore FPGA device on NX1H35AS-EK evaluation kit equipped by an analog front-end bread board in the frame of the GSTP De-Risk funded project.
The provided open-source/open-hardware design files which allows to synthesis of the converter control logic for multiple resolutions and sample rates according to actual target applications requirements. The analog front end KiCAD data are provided as well (see the project GIT repository
The original simple design used on customer or industrial grade FPGAs was able to realize resolution about 14 bits by only single external operational amplifier per channel. In the combination with precise (chopper stabilized) amplifiers, analog switches and comparator resolution better than 20 bits has been obtained in the past.
Very limited portfolio of analog components (operation amplifiers, analog switches, precise voltage refernces) with space qualification was major obstacle during the porting to space grade components and radiation-tolerant NanoXplore FPGAs. It complicated design of the analog front-end and change of the input bias and offset currents contributed to conversion characteristics shift and slope changes over temperature tested range -40 to 85°C more than expected. As the most promising has been found Texas Instruments chip equivalent to their OPA4H014-SEP operational amplifier introduced into their space portfolio at the end of the 2021 year.
The PiKRON company designed system has been evaluated at Laboratory of Precise Measurement of Electrical Quantities (METLAB) of Czech Technical University in Prague, FEE. The complete setup for static characterization with two Keysight 3458A voltmeters, Keysight B2912A source meter and climate chamber ClimaEvent C/180/70/3 has been orchestrated over GPIB from PC unit with CTU developed automation scripts using open Phython components. The Stanford Research Systems DS 360 generator has been used in addition for dynamic characterization. The full 8 channel modulator datastream has been delivered from NanoXplore FPGA to Xilinx Zynq 7000 bases MZ_APO kit which captured and precomputed modulator data stream on PC system TCP request and sent response with data back to the central Python based control system.
The achieved results confirms that design provides enhance of resolution when moving average from n samples is used which is directly proportional to the number of samples (i.e. 1/n noise suppression) up to the limit caused probably by analog reference switch and FPGA clock jitter in range of 25 ps. The expected linearity has been achieved but temperature stability requires further design phase. The secondary/experiment goal to design high-resolution Sum-Int ADC conversion frot-end based on space qualified components was not successful at the first trial. The found problems and components limits will be presented as well.

The actual PiKRON's Sum-Int ADC technique has been introduced in the paper:
PÍŠA, Pavel; PORAZIL, Petr. Σ-Integration Analog to Digital Converter, Idea, Implementation and Results. IFAC Proceedings Volumes, 2005, 38.1: 85-90., Congress of the International Federation of Automatic Control. 16th IFAC World Congress: article online

Primary authors

Mr Pavel Pisa (PiKRON s.r.o.) Mr Petr Porazil (PiKRON s.r.o.) Mr Jakub Ladman Mr David Levacq (ESTEC) Mr Marek Peca (ESTEC) Mr Radek Sedlacek (Czech Technical University in Prague, FEE K13138) Mr Michal Spacek (Czech Technical University in Prague, FEE K13138)

Presentation materials